library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity Divider is
    Generic (
        N : integer := 8  -- Number of bits for dividend and divisor
    );
    Port (
        clk     : in  std_logic;              -- Clock signal
        reset   : in  std_logic;              -- Reset signal
        start   : in  std_logic;              -- Start signal
        dividend: in  std_logic_vector(N-1 downto 0); -- Dividend input
        divisor : in  std_logic_vector(N-1 downto 0); -- Divisor input
        quotient: out std_logic_vector(N-1 downto 0); -- Quotient output
        remainder: out std_logic_vector(N-1 downto 0); -- Remainder output
        done    : out std_logic               -- Done flag
    );
end Divider;
 
architecture Behavioral of Divider is
    signal dividend_reg : unsigned(N downto 0); -- Dividend register (N+1 bits for shifting)
    signal divisor_reg  : unsigned(N downto 0); -- Divisor register (N+1 bits)
    signal remainder_reg: unsigned(N downto 0); -- Remainder register
    signal quotient_reg : unsigned(N-1 downto 0); -- Quotient register
    signal count        : integer range 0 to N := 0; -- Bit counter
    signal busy         : std_logic := '0'; -- Busy flag
begin
 
    process(clk, reset)
    begin
        if reset = '1' then
            -- Reset all signals
            dividend_reg <= (others => '0');
            divisor_reg <= (others => '0');
            remainder_reg <= (others => '0');
            quotient_reg <= (others => '0');
            count <= 0;
            busy <= '0';
            done <= '0';
        elsif rising_edge(clk) then
            if start = '1' and busy = '0' then
                -- Initialize registers
                dividend_reg <= unsigned('0' & dividend); -- Extend dividend to N+1 bits
                divisor_reg <= unsigned('0' & divisor);   -- Extend divisor to N+1 bits
                remainder_reg <= (others => '0');
                quotient_reg <= (others => '0');
                count <= N;
                busy <= '1';
                done <= '0';
            elsif busy = '1' then
                if count > 0 then
                    -- Shift left the remainder and quotient
                    remainder_reg <= remainder_reg(N-1 downto 0) & dividend_reg(N-1);
                    dividend_reg <= dividend_reg(N-2 downto 0) & '0';
 
                    -- Subtract divisor from remainder
                    if remainder_reg >= divisor_reg then
                        remainder_reg <= remainder_reg - divisor_reg;
                        quotient_reg(count-1) <= '1';
                    else
                        quotient_reg(count-1) <= '0';
                    end if;
 
                    -- Decrement bit counter
                    count <= count - 1;
                else
                    -- Division complete
                    busy <= '0';
                    done <= '1';
                end if;
            end if;
        end if;
    end process;
 
    -- Map outputs
    quotient <= std_logic_vector(quotient_reg);
    remainder <= std_logic_vector(remainder_reg(N-1 downto 0));
 
end Behavioral;

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