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  1. #define MAIN 1
  2.  
  3. #include "system_defines.h"
  4. #include "cyclone_device.h"
  5. #include "pmbus_commands.h"
  6. #include "pmbus.h"
  7. #include "variables.h"
  8. #include "function_definitions.h"
  9. #include "software_interrupts.h"
  10. #include "cyclone_defines.h"
  11. #include "stdio.h"
  12.  
  13. #define PERIOD         (40000) // 4 Ghz high speed clock/100 KHz switching frequency = 40000.
  14.  
  15. //to jumper 64 pin open loop board for fake power supply feed back
  16. //
  17. //  J22 pins 2 to 3 - DPWM0A to FLTRDPWM0
  18. // J11 pins 1 to 2 - FLTRDPWM0 to voltage loop feedback
  19. // j7 pins 1 to 2 - voltage loop feedback to EAP0
  20.  
  21. int ram_eadcdac; 
  22. // comment for hyperknob [min=0, max=16383, step=256]
  23.  
  24.  
  25. void init_front_end0(void)
  26. {
  27. 	FeCtrl0Regs.EADCDAC.bit.DAC_VALUE = 0;
  28. 	FeCtrl0Regs.EADCCTRL.bit.AFE_GAIN = 2;
  29. 	FeCtrl0Regs.EADCCTRL.bit.EADC_MODE=3;			// continue SAR mode =3
  30. }
  31.  
  32. void init_front_end1(void)//for CT1 sensing
  33. {
  34. 	FeCtrl1Regs.EADCDAC.bit.DAC_VALUE = 0;
  35. 	FeCtrl1Regs.EADCCTRL.bit.AFE_GAIN = 2;
  36. 	FeCtrl1Regs.EADCCTRL.bit.EADC_MODE=3;			// continue SAR mode =3
  37. }
  38.  
  39. void init_front_end2(void)//for CT2 sensing
  40. {
  41. 	FeCtrl2Regs.EADCDAC.bit.DAC_VALUE = 0;
  42. 	FeCtrl2Regs.EADCCTRL.bit.AFE_GAIN = 2;
  43. 	FeCtrl2Regs.EADCCTRL.bit.EADC_MODE=3;			// continue SAR mode =3
  44. }
  45.  
  46. void init_front_ends(void)
  47. {
  48. 	init_front_end0();
  49. 	init_front_end1();
  50. 	init_front_end2();
  51. }
  52. void init_dpwm0(void) 
  53. {
  54.  
  55.     Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 0;     //disable locally for init
  56. 	Dpwm0Regs.DPWMCTRL0.bit.CLA_EN = 1;		//default is 1 - use cla
  57.  
  58. 	Dpwm0Regs.DPWMCTRL0.bit.PWM_MODE = 0; //normal mode
  59. 	Dpwm0Regs.DPWMPRD.all = PERIOD;         //use .all for all values, make sure scaling matches.
  60. 	Dpwm0Regs.DPWMEV1.all = 0;              //Put event 1 at start of period
  61. 	Dpwm0Regs.DPWMEV2.all = PERIOD/4;       //1/4 of period - divide is OK because it's all constants.
  62. 	Dpwm0Regs.DPWMEV3.all = PERIOD/2;       //1/2 of period   
  63. 	Dpwm0Regs.DPWMEV4.all = (PERIOD * 3)/4; //3/4 of period
  64. 	Dpwm0Regs.DPWMSAMPTRIG1.all = (PERIOD * 3)/4; //3/4 of period
  65.  
  66. 	Dpwm0Regs.DPWMCTRL2.bit.SAMPLE_TRIG_1_EN = 1; //enable 1 sample trigger
  67. 	Dpwm0Regs.DPWMCTRL1.bit.EVENT_UP_SEL = 1; //update at end of period
  68.  
  69.     Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 1;     //enable locally
  70.  
  71. }
  72.  
  73. void init_filter0(void)
  74. {
  75.  
  76. //PID setup taken from a random topology - lab is for closing loop, not tuning parameters.
  77.  
  78. 	Filter0Regs.FILTERKPCOEF0.bit.KP_COEF_0 = 800;
  79.  
  80. 	Filter0Regs.FILTERKICOEF0.bit.KI_COEF_0 = 50;
  81.  
  82. 	Filter0Regs.FILTERKDCOEF0.bit.KD_COEF_0 = 1500;
  83.  
  84. 	Filter0Regs.FILTERKDALPHA.bit.KD_ALPHA_0 = -1;
  85.  
  86. 	Filter0Regs.FILTERKICLPHI.bit.KI_CLAMP_HIGH = 0x7FFFFF;
  87.     Filter0Regs.FILTERKICLPLO.bit.KI_CLAMP_LOW = 0;
  88.  
  89. 	Filter0Regs.FILTEROCLPHI.bit.OUTPUT_CLAMP_HIGH = 0x7FFFFF;
  90. 	Filter0Regs.FILTEROCLPLO.bit.OUTPUT_CLAMP_LOW = 0;
  91.  
  92.     Filter0Regs.FILTERCTRL.bit.FILTER_EN = 1;
  93.      //enable OK here, because nothing will happen until DPWM and front end are globally enabled
  94.  
  95. 	//Better option for handling shoot through - uses full dynamic range of filter
  96.  
  97. 	LoopMuxRegs.FILTERKCOMPA.bit.KCOMP0 = (PERIOD/2) >> 4; //KCOMP is at 4 ns, period is at 250 ps
  98. 	Filter0Regs.FILTERCTRL.bit.OUTPUT_MULT_SEL =3; //select half period kcomp for output multiplier
  99.  
  100. }
  101.  
  102. void init_filter1(void)
  103. {
  104.  
  105. //PID setup taken from a random topology - lab is for closing loop, not tuning parameters.
  106.  
  107. 	Filter1Regs.FILTERKPCOEF0.bit.KP_COEF_0 = 800;
  108.  
  109. 	Filter1Regs.FILTERKICOEF0.bit.KI_COEF_0 = 50;
  110.  
  111. 	Filter1Regs.FILTERKDCOEF0.bit.KD_COEF_0 = 1500;
  112.  
  113. 	Filter1Regs.FILTERKDALPHA.bit.KD_ALPHA_0 = -1;
  114.  
  115. 	Filter1Regs.FILTERKICLPHI.bit.KI_CLAMP_HIGH = 0x7FFFFF;
  116.     Filter1Regs.FILTERKICLPLO.bit.KI_CLAMP_LOW = 0;
  117.  
  118. 	Filter1Regs.FILTEROCLPHI.bit.OUTPUT_CLAMP_HIGH = 0x7FFFFF;
  119. 	Filter1Regs.FILTEROCLPLO.bit.OUTPUT_CLAMP_LOW = 0;
  120.  
  121.     Filter1Regs.FILTERCTRL.bit.FILTER_EN = 1;
  122.      //enable OK here, because nothing will happen until DPWM and front end are globally enabled
  123.  
  124. 	//Better option for handling shoot through - uses full dynamic range of filter
  125.  
  126. 	LoopMuxRegs.FILTERKCOMPA.bit.KCOMP0 = (PERIOD/2) >> 4; //KCOMP is at 4 ns, period is at 250 ps
  127. 	Filter1Regs.FILTERCTRL.bit.OUTPUT_MULT_SEL = 3; //select half period kcomp for output multiplier
  128.  
  129. }
  130. void init_filter2(void)
  131. {
  132.  
  133. //PID setup taken from a random topology - lab is for closing loop, not tuning parameters.
  134.  
  135. 	Filter2Regs.FILTERKPCOEF0.bit.KP_COEF_0 = 800;
  136.  
  137. 	Filter2Regs.FILTERKICOEF0.bit.KI_COEF_0 = 50;
  138.  
  139. 	Filter2Regs.FILTERKDCOEF0.bit.KD_COEF_0 = 1500;
  140.  
  141. 	Filter2Regs.FILTERKDALPHA.bit.KD_ALPHA_0 = -1;
  142.  
  143. 	Filter2Regs.FILTERKICLPHI.bit.KI_CLAMP_HIGH = 0x7FFFFF;
  144.     Filter2Regs.FILTERKICLPLO.bit.KI_CLAMP_LOW = 0;
  145.  
  146. 	Filter2Regs.FILTEROCLPHI.bit.OUTPUT_CLAMP_HIGH = 0x7FFFFF;
  147. 	Filter2Regs.FILTEROCLPLO.bit.OUTPUT_CLAMP_LOW = 0;
  148.  
  149.     Filter2Regs.FILTERCTRL.bit.FILTER_EN = 1;
  150.      //enable OK here, because nothing will happen until DPWM and front end are globally enabled
  151.  
  152. 	//Better option for handling shoot through - uses full dynamic range of filter
  153.  
  154. 	LoopMuxRegs.FILTERKCOMPA.bit.KCOMP0 = (PERIOD/2) >> 4; //KCOMP is at 4 ns, period is at 250 ps
  155. 	Filter2Regs.FILTERCTRL.bit.OUTPUT_MULT_SEL = 3; //select half period kcomp for output multiplier
  156.  
  157. }
  158. void init_loop_mux(void)
  159. {
  160. 	LoopMuxRegs.DPWMMUX.bit.DPWM0_FILTER_SEL = 0; //use filter 0 for DPWM 0
  161.  
  162. 	LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM0_EN = 1; //use DPWM0 for filter0 sample trigger
  163.  
  164. 	LoopMuxRegs.FECTRL0MUX.bit.DPWM0_FRAME_SYNC_EN = 1; //trigger ramp steps with DPWM0 frame sync
  165. }
  166. void init_loop_mux1(void)
  167. {
  168. 	LoopMuxRegs.DPWMMUX.bit.DPWM0_FILTER_SEL = 1; //use filter 0 for DPWM 0
  169.  
  170. 	LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM0_EN = 1; //use DPWM0 for filter0 sample trigger
  171.  
  172. 	LoopMuxRegs.FECTRL0MUX.bit.DPWM0_FRAME_SYNC_EN = 1; //trigger ramp steps with DPWM0 frame sync
  173. }
  174. void global_enable(void)
  175. {
  176. 	union GLBEN_REG glben_store; //collect global enable bits for simultaneous use
  177.  
  178. 	glben_store.all = 0;
  179.  
  180. 	glben_store.bit.DPWM0_EN = 1;
  181.  
  182. 	glben_store.bit.FE_CTRL0_EN = 1;
  183. 	glben_store.bit.FE_CTRL1_EN = 1;
  184. 	glben_store.bit.FE_CTRL2_EN = 1;
  185.  
  186. 	LoopMuxRegs.GLBEN = glben_store;
  187. }
  188.  
  189. void ramp_up0(void)
  190. {
  191. 	FeCtrl0Regs.RAMPCTRL.bit.FIRMWARE_START = 0; //clear it to make sure we get a rising edge
  192. 	FeCtrl0Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = 0x3fff; //ramp up to the top
  193. 	FeCtrl0Regs.DACSTEP.bit.DAC_STEP = 0x40; //make it slow for a while
  194. 	FeCtrl0Regs.EADCDAC.bit.DAC_VALUE = 0x2; //start at the lowest safe value
  195. 	FeCtrl0Regs.RAMPCTRL.bit.RAMP_EN = 1;
  196. 	FeCtrl0Regs.RAMPCTRL.bit.FIRMWARE_START = 1; //start it.
  197.  
  198. }
  199. void ramp_up1(void)
  200. {
  201. 	FeCtrl1Regs.RAMPCTRL.bit.FIRMWARE_START = 0; //clear it to make sure we get a rising edge
  202. 	FeCtrl1Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = 0x3fff; //ramp up to the top
  203. 	FeCtrl1Regs.DACSTEP.bit.DAC_STEP = 0x40; //make it slow for a while
  204. 	FeCtrl1Regs.EADCDAC.bit.DAC_VALUE = 0x2; //start at the lowest safe value
  205. 	FeCtrl1Regs.RAMPCTRL.bit.RAMP_EN = 1;
  206. 	FeCtrl1Regs.RAMPCTRL.bit.FIRMWARE_START = 1; //start it.
  207.  
  208. }
  209. void ramp_up2(void)
  210. {
  211. 	FeCtrl2Regs.RAMPCTRL.bit.FIRMWARE_START = 0; //clear it to make sure we get a rising edge
  212. 	FeCtrl2Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = 0x3fff; //ramp up to the top
  213. 	FeCtrl2Regs.DACSTEP.bit.DAC_STEP = 0x40; //make it slow for a while
  214. 	FeCtrl2Regs.EADCDAC.bit.DAC_VALUE = 0x2; //start at the lowest safe value
  215. 	FeCtrl2Regs.RAMPCTRL.bit.RAMP_EN = 1;
  216. 	FeCtrl2Regs.RAMPCTRL.bit.FIRMWARE_START = 1; //start it.
  217.  
  218. }
  219. void ramp_down0(void)
  220. {
  221. 	FeCtrl0Regs.RAMPCTRL.bit.FIRMWARE_START = 0; //clear it to make sure we get a rising edge
  222. 	FeCtrl0Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = 0x2;//finish at the lowest safe value
  223. 	FeCtrl0Regs.DACSTEP.bit.DAC_STEP = 0x40; //make it slow for a while
  224. 	FeCtrl0Regs.EADCDAC.bit.DAC_VALUE = 0x3fff; //ramp down from the top
  225. 	FeCtrl0Regs.RAMPCTRL.bit.RAMP_EN = 1;
  226. 	FeCtrl0Regs.RAMPCTRL.bit.FIRMWARE_START = 1; //start it.
  227.  
  228. }
  229. void ramp_down1(void)
  230. {
  231. 	FeCtrl1Regs.RAMPCTRL.bit.FIRMWARE_START = 0; //clear it to make sure we get a rising edge
  232. 	FeCtrl1Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = 0x2;//finish at the lowest safe value
  233. 	FeCtrl1Regs.DACSTEP.bit.DAC_STEP = 0x40; //make it slow for a while
  234. 	FeCtrl1Regs.EADCDAC.bit.DAC_VALUE = 0x3fff; //ramp down from the top
  235. 	FeCtrl1Regs.RAMPCTRL.bit.RAMP_EN = 1;
  236. 	FeCtrl1Regs.RAMPCTRL.bit.FIRMWARE_START = 1; //start it.
  237.  
  238. }
  239. void ramp_down2(void)
  240. {
  241. 	FeCtrl2Regs.RAMPCTRL.bit.FIRMWARE_START = 0; //clear it to make sure we get a rising edge
  242. 	FeCtrl2Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = 0x2;//finish at the lowest safe value
  243. 	FeCtrl2Regs.DACSTEP.bit.DAC_STEP = 0x40; //make it slow for a while
  244. 	FeCtrl2Regs.EADCDAC.bit.DAC_VALUE = 0x3fff; //ramp down from the top
  245. 	FeCtrl2Regs.RAMPCTRL.bit.RAMP_EN = 1;
  246. 	FeCtrl2Regs.RAMPCTRL.bit.FIRMWARE_START = 1; //start it.
  247.  
  248. }
  249.  
  250. void wait_for_ramp_end(void)
  251. {
  252. 	volatile int i;
  253. 	while(FeCtrl0Regs.RAMPSTAT.bit.RAMP_BUSY == 1)
  254. 	{
  255. 		pmbus_handler();
  256. 	}
  257. }
  258.  
  259. void init_timer_interrupt(void)
  260. {
  261. 	TimerRegs.T16PWM2CMP0DAT.all = 1562;  	//Threshold to reset counter - 15.625 mHz/10 KHz.
  262. 	TimerRegs.T16PWM2CMPCTRL.all = 2;		//Enables compare 0 (reset) interrupt
  263. 	TimerRegs.T16PWM2CNTCTRL.all = 0x00c;	//PWM counter is running & enables PWM counter reset by compare action on compare 0
  264.  
  265. 	write_reqmask(CIMINT_ALL_PWM2_COMP); //enable pwm2cmp 
  266.  
  267. 	enable_interrupt();
  268. }
  269.  
  270. void init_ADC_polled(void)
  271. {
  272. 	AdcRegs.ADCCTRL.bit.MAX_CONV = 6;       // A total of 5 conversions (0 to 4)
  273. 	AdcRegs.ADCCTRL.bit.SINGLE_SWEEP = 1;
  274. 	AdcRegs.ADCCTRL.bit.ADC_EN = 1;
  275. 	AdcRegs.ADCSEQSEL0.bit.SEQ0 = 0;        // ad00 AC-L		order0
  276. 	AdcRegs.ADCSEQSEL0.bit.SEQ1 = 2;        // AD01 IIN
  277. 	AdcRegs.ADCSEQSEL0.bit.SEQ2 = 3;        // AD03 VB
  278. 	AdcRegs.ADCSEQSEL0.bit.SEQ3 = 4;        // ad04  AC-N
  279. 	AdcRegs.ADCSEQSEL1.bit.SEQ4 = 6;        // ad06  CT-1		order4
  280. 	AdcRegs.ADCSEQSEL1.bit.SEQ5 = 7;        // ad07  VB-OV
  281. 	AdcRegs.ADCSEQSEL1.bit.SEQ6 = 13;        // ad13 CT-2 
  282. 	AdcRegs.ADCSEQSEL1.bit.SEQ7 = 9;        // ad09
  283. 	AdcRegs.ADCSEQSEL2.bit.SEQ8 = 13;        // ad13 
  284.  
  285.  
  286. 	AdcRegs.ADCAVGCTRL.bit.AVG0_CONFIG = 0; // Average 4 samples of ad06
  287. 	AdcRegs.ADCAVGCTRL.bit.AVG0_EN = 1;     // Module0 averaging enabled
  288. 	AdcRegs.ADCAVGCTRL.bit.AVG1_CONFIG = 1; // Average 8 samples of AD02
  289. 	AdcRegs.ADCAVGCTRL.bit.AVG1_EN = 1;     // Module1 averaging enabled
  290. 	AdcRegs.ADCAVGCTRL.bit.AVG2_CONFIG = 2; // Average 16 samples of AD04
  291. 	AdcRegs.ADCAVGCTRL.bit.AVG2_EN = 1;     // Module2 averaging enabled
  292. 	AdcRegs.ADCAVGCTRL.bit.AVG3_CONFIG = 3; // Average 32 samples of ad06
  293. 	AdcRegs.ADCAVGCTRL.bit.AVG3_EN = 1;     // Module3 averaging enabled
  294. 	AdcRegs.ADCAVGCTRL.bit.AVG4_CONFIG = 3; // Average 4 samples  of ad08
  295. 	AdcRegs.ADCAVGCTRL.bit.AVG4_EN = 1;     // Module4 averaging enabled
  296. 	AdcRegs.ADCAVGCTRL.bit.AVG5_CONFIG = 3; // Average 4 samples  of ad08
  297. 	AdcRegs.ADCAVGCTRL.bit.AVG5_EN = 1;     // Module4 averaging enabled
  298.  
  299. 	AdcRegs.ADCCTRL.bit.SW_START = 1;  // trigger a new measurement sequence
  300.  
  301. 	ad02_raw_min = ad06_raw_min = ad06B_raw_min = ad04_raw_min = ad08_raw_min = 0xFFF; //initialize minimums to maximum value
  302. 	ad02_avg_min = ad06_avg_min = ad06B_avg_min = ad04_avg_min = ad08_avg_min = 0xFFF;
  303.  
  304. }
  305.  
  306. void main()
  307. {
  308. 	if(MiscAnalogRegs.GLBIOREAD.bit.TDO_IO_READ == 0) //emergency backdoor - TMS is normally pulled up by external resistor
  309. 	{
  310. 		clear_integrity_word();  //if it's pulled down, clear checksum (integrity word)
  311. 	}
  312.  
  313. //	GioRegs.FAULTDIR.bit.FLT0_DIR = 1; //make fault 0 an output for instrumentation
  314.  
  315. 	init_pmbus();
  316. 	init_ADC_polled();
  317. 	init_dpwm0();
  318. 	init_front_ends();
  319. 	//init_filter0();
  320. 	init_loop_mux1();
  321. 	//init_front_end0();
  322. 	init_front_ends();
  323. 	global_enable();
  324. 	init_timer_interrupt();
  325. 	for(;;)
  326. 	{
  327. 		ramp_up0();
  328. 		ramp_up1();
  329. 		ramp_up2();
  330. 		wait_for_ramp_end();
  331.  
  332. 		ramp_down0();
  333. 		ramp_down1();
  334. 		ramp_down2();
  335. 		wait_for_ramp_end();
  336. 	}
  337. }
  338.  
  339. #pragma INTERRUPT(c_int00,RESET)
  340.  
  341. void c_int00(void)
  342. {
  343. 	main();
  344. }
  345.  
Compilation error #stdin compilation error #stdout 0s 0KB
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compilation info 
prog.c:3:28: fatal error: system_defines.h: No such file or directory
 #include "system_defines.h"
                            ^
compilation terminated.
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https://ideone.com/qHQevt
UCD3138 ADC/EADC vlaue
language:
C (gcc 8.3)
created:
10 years ago
visibility:
secret

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