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  1. /*
  2.  * File: TempSensor.c
  3.  * Author: narayan
  4.  *
  5.  * Created on 15 de Março de 2019, 22:29
  6.  */
  7.  
  8. #ifndef F_CPU
  9. # define F_CPU 20000000UL / 8
  10. #endif
  11.  
  12. #include <stdlib.h>
  13. #include <inttypes.h>
  14. #include <avr/io.h>
  15. #include <util/delay.h>
  16. #include <string.h>
  17.  
  18. #include "usart.h"
  19.  
  20. /*
  21.  *
  22.  */
  23.  
  24. #define WRITE_OP (0x00 << 0x00)
  25. #define READ_OP (0x01 << 0x00)
  26.  
  27. //Statuses handling
  28. #define STATUS_NACK 0x01
  29. #define STATUS_ACK 0x00
  30. #define STATUS_OK 0x00
  31.  
  32. void CPU_Init(void){
  33. // Enable Protected registers write
  34. CPU_CCP = CCP_IOREG_gc;
  35. CLKCTRL_MCLKCTRLA = CLKCTRL_CLKSEL_OSC20M_gc;
  36.  
  37. // Disable Prescaler
  38. CPU_CCP = CCP_IOREG_gc;
  39. CLKCTRL_MCLKCTRLB = CLKCTRL_PDIV_8X_gc | CLKCTRL_PEN_bm;
  40. }
  41.  
  42. void TWI_Init(void){
  43. TWI0_CTRLA |= TWI_SDASETUP_4CYC_gc // SDASETUP time of 4 clock cycles
  44. | TWI_SDAHOLD_500NS_gc; // SDA Hold time - Meets SMBus specifications across all corners (0x03) ???
  45. TWI0_CTRLA &= ~TWI_FMPEN_bm; // Fast Mode Plus disabled
  46.  
  47. // Set MBAUD to get 100KHz for SCL from fSCL = CLK_PER / (10 + 2*BAUD + CLK_PER*tRise)
  48. // fSCL = 104KHz, CLK_PER = 20MHz/8, tRise = 2.5ns (datasheet page 17)
  49. TWI0_MBAUD = 0x07;
  50. TWI0_CTRLA &= ~TWI_TIMEOUT0_bm; // Disable Timeout for TWI operation
  51. TWI0_MSTATUS = TWI_BUSSTATE_IDLE_gc; // Manually set the Bus state to IDLE for TWI operation
  52. TWI0_MCTRLA = TWI_ENABLE_bm; // Enable Master Mode of operation
  53. }
  54.  
  55. void Start_Bit(void){
  56. // Wait until BUS is IDLE
  57. while( (TWI0_MSTATUS & TWI_BUSSTATE_gm) == TWI_BUSSTATE_BUSY_gc)
  58. /*wait*/;
  59.  
  60. // Send Start Bit
  61. TWI0_MCTRLB = TWI_MCMD_REPSTART_gc;
  62. }
  63.  
  64. void Stop_Bit(void){
  65. // Wait until BUS is IDLE
  66. while( (TWI0_MSTATUS & TWI_BUSSTATE_gm) == TWI_BUSSTATE_BUSY_gc)
  67. /*wait*/;
  68.  
  69. TWI0_MCTRLB = TWI_MCMD_STOP_gc;
  70. }
  71.  
  72. uint8_t TWI_Read(uint8_t sl_addr, uint8_t* packet){
  73.  
  74. while((TWI0_MSTATUS & TWI_BUSSTATE_BUSY_gc) == TWI_BUSSTATE_BUSY_gc)
  75. /*wait*/;
  76.  
  77. // Send Slave address and R operation onto the bus
  78. TWI0_MADDR = (sl_addr << 1) | READ_OP;
  79.  
  80. // Check Slave device ACK/NACK bit to signal address not/acknowledgment
  81. if(TWI0_MSTATUS & TWI_RXACK_bm){
  82. return STATUS_NACK; // Slave Address NOT received
  83. }
  84.  
  85. // Data byte is stored into TWI0_DATA register and passed to *packet variable
  86. *packet = TWI0_MDATA;
  87. TWI0_MCTRLB = TWI_ACKACT_ACK_gc;
  88.  
  89. // Check Master device ACK/NACK bit to signal data not/acknowledgment
  90. //if (TWI0_MSTATUS & TWI_RXACK_bm)
  91. //return STATUS_NACK;
  92.  
  93. return STATUS_OK;
  94. }
  95.  
  96. int main(int argc, char** argv) {
  97. uint8_t temperature[256] = {0};
  98. uint8_t sumtemp = 0;
  99. float avgtemp = 0.0;
  100. char message[256];
  101.  
  102. CPU_Init();
  103. USART2_Init();
  104. TWI_Init();
  105.  
  106. while(0x01){
  107. for(uint8_t i = 0; i < 256; i++){
  108. TWI_Read(0x18, &temperature[i]);
  109. sumtemp += temperature[i];
  110. }
  111. // Send NACK from Master to signal don't need more data
  112. TWI0_MCTRLB = TWI_ACKACT_NACK_gc;
  113. // Send Stop bit to terminate transaction
  114. TWI0_MCTRLB = TWI_MCMD_STOP_gc;
  115. avgtemp = sumtemp / 256.0;
  116. USART2_SendStr(itoa(avgtemp, message, 10));
  117. USART2_SendChar('\n');
  118. _delay_ms(1000);
  119. }
  120.  
  121. return (EXIT_SUCCESS);
  122. }
Compilation error #stdin compilation error #stdout 0s 0KB
stdin
Standard input is empty
compilation info
prog.c:15:20: fatal error: avr/io.h: No such file or directory
 #include <avr/io.h>
                    ^
compilation terminated.
stdout
Standard output is empty