---------------------------------------------------------------------------------- -- Company: -- Engineer: Mr.DDDAlKilanny -- -- Create Date: 16:29:19 03/22/2013 -- Design Name: -- Module Name: RegisterFile - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.mine.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity RegisterFile is port ( -- selector of mux1 read_sel1 : in std_logic_vector(4 downto 0); -- selector of mux2 read_sel2 : in std_logic_vector(4 downto 0); -- selector for destination register to write into write_sel : in std_logic_vector(4 downto 0); -- the write-enable for registers write_ena : in std_logic; -- the clock clk: in std_logic; -- the write data for destination register write_data: in std_logic_vector(31 downto 0); -- the output of mux1 data1: out std_logic_vector(31 downto 0); -- the output of mux2 data2: out std_logic_vector(31 downto 0) ); end RegisterFile; architecture Behavioral of RegisterFile is signal decout, reg1out, reg2out, reg3out, reg4out, reg5out, reg6out, reg7out, reg8out, reg9out, reg10out, reg11out, reg12out, reg13out, reg14out, reg15out, reg16out, reg17out, reg18out, reg19out, reg20out, reg21out, reg22out, reg23out, reg24out, reg25out, reg26out, reg27out, reg28out, reg29out, reg30out, reg31out, reg32out : std_logic_vector (31 downto 0); signal canwrite1, canwrite2, canwrite3, canwrite4, canwrite5, canwrite6, canwrite7, canwrite8, canwrite9, canwrite10, canwrite11, canwrite12, canwrite13, canwrite14, canwrite15, canwrite16, canwrite17, canwrite18, canwrite19, canwrite20, canwrite21, canwrite22, canwrite23, canwrite24, canwrite25, canwrite26, canwrite27, canwrite28, canwrite29, canwrite30, canwrite31, canwrite32 : std_logic; begin -- selects which register to write into -- in, enable, out D : dec port map (write_sel, '1', decout); -- in_data, out_data, clk, write_ena, inc, clr R1 : reg port map (write_data, reg1out, clk, canwrite1, '0', '0'); R2 : reg port map (write_data, reg2out, clk, canwrite2, '0', '0'); R3 : reg port map (write_data, reg3out, clk, canwrite3, '0', '0'); R4 : reg port map (write_data, reg4out, clk, canwrite4, '0', '0'); R5 : reg port map (write_data, reg5out, clk, canwrite5, '0', '0'); R6 : reg port map (write_data, reg6out, clk, canwrite6, '0', '0'); R7 : reg port map (write_data, reg7out, clk, canwrite7, '0', '0'); R8 : reg port map (write_data, reg8out, clk, canwrite8, '0', '0'); R9 : reg port map (write_data, reg9out, clk, canwrite9, '0', '0'); R10 : reg port map (write_data, reg10out, clk, canwrite10, '0', '0'); R11 : reg port map (write_data, reg11out, clk, canwrite11, '0', '0'); R12 : reg port map (write_data, reg12out, clk, canwrite12, '0', '0'); R13 : reg port map (write_data, reg13out, clk, canwrite13, '0', '0'); R14 : reg port map (write_data, reg14out, clk, canwrite14, '0', '0'); R15 : reg port map (write_data, reg15out, clk, canwrite15, '0', '0'); R16 : reg port map (write_data, reg16out, clk, canwrite16, '0', '0'); R17 : reg port map (write_data, reg17out, clk, canwrite17, '0', '0'); R18 : reg port map (write_data, reg18out, clk, canwrite18, '0', '0'); R19 : reg port map (write_data, reg19out, clk, canwrite19, '0', '0'); R20 : reg port map (write_data, reg20out, clk, canwrite20, '0', '0'); R21 : reg port map (write_data, reg21out, clk, canwrite21, '0', '0'); R22 : reg port map (write_data, reg22out, clk, canwrite22, '0', '0'); R23 : reg port map (write_data, reg23out, clk, canwrite23, '0', '0'); R24 : reg port map (write_data, reg24out, clk, canwrite24, '0', '0'); R25 : reg port map (write_data, reg25out, clk, canwrite25, '0', '0'); R26 : reg port map (write_data, reg26out, clk, canwrite26, '0', '0'); R27 : reg port map (write_data, reg27out, clk, canwrite27, '0', '0'); R28 : reg port map (write_data, reg28out, clk, canwrite28, '0', '0'); R29 : reg port map (write_data, reg29out, clk, canwrite29, '0', '0'); R30 : reg port map (write_data, reg30out, clk, canwrite30, '0', '0'); R31 : reg port map (write_data, reg31out, clk, canwrite31, '0', '0'); R32 : reg port map (write_data, reg32out, clk, canwrite32, '0', '0'); -- selects which register to read from -- I0, I1, ..., I30, I31, selector, output, enable M1 : mux port map (reg1out, reg2out, reg3out, reg4out, reg5out, reg6out, reg7out, reg8out, reg9out, reg10out, reg11out, reg12out, reg13out, reg14out, reg15out, reg16out, reg17out, reg18out, reg19out, reg20out, reg21out, reg22out, reg23out, reg24out, reg25out, reg26out, reg27out, reg28out, reg29out, reg30out, reg31out, reg32out, read_sel1, data1, '1'); M2 : mux port map (reg1out, reg2out, reg3out, reg4out, reg5out, reg6out, reg7out, reg8out, reg9out, reg10out, reg11out, reg12out, reg13out, reg14out, reg15out, reg16out, reg17out, reg18out, reg19out, reg20out, reg21out, reg22out, reg23out, reg24out, reg25out, reg26out, reg27out, reg28out, reg29out, reg30out, reg31out, reg32out, read_sel2, data2, '1'); process (clk) begin if (clk'event and clk = '0') then canwrite1 <= write_ena and decout(0); canwrite2 <= write_ena and decout(1); canwrite3 <= write_ena and decout(2); canwrite4 <= write_ena and decout(3); canwrite5 <= write_ena and decout(4); canwrite6 <= write_ena and decout(5); canwrite7 <= write_ena and decout(6); canwrite8 <= write_ena and decout(7); canwrite9 <= write_ena and decout(8); canwrite10 <= write_ena and decout(9); canwrite11 <= write_ena and decout(10); canwrite12 <= write_ena and decout(11); canwrite13 <= write_ena and decout(12); canwrite14 <= write_ena and decout(13); canwrite15 <= write_ena and decout(14); canwrite16 <= write_ena and decout(15); canwrite17 <= write_ena and decout(16); canwrite18 <= write_ena and decout(17); canwrite19 <= write_ena and decout(18); canwrite20 <= write_ena and decout(19); canwrite21 <= write_ena and decout(20); canwrite22 <= write_ena and decout(21); canwrite23 <= write_ena and decout(22); canwrite24 <= write_ena and decout(23); canwrite25 <= write_ena and decout(24); canwrite26 <= write_ena and decout(25); canwrite27 <= write_ena and decout(26); canwrite28 <= write_ena and decout(27); canwrite29 <= write_ena and decout(28); canwrite30 <= write_ena and decout(29); canwrite31 <= write_ena and decout(30); canwrite32 <= write_ena and decout(31); end if; end process; end Behavioral;