RCC->CR |= RCC_CR_HSEON;
 80001f6:	4b24      	ldr	r3, [pc, #144]	; (8000288 <clock_init+0x94>)
 80001f8:	681a      	ldr	r2, [r3, #0]
 80001fa:	f442 3280 	orr.w	r2, r2, #65536	; 0x10000
 80001fe:	601a      	str	r2, [r3, #0]
	while( !(RCC->CR & RCC_CR_HSERDY) ){}
 8000200:	681a      	ldr	r2, [r3, #0]
 8000202:	0391      	lsls	r1, r2, #14
 8000204:	d5fc      	bpl.n	8000200 <clock_init+0xc>

	FLASH->ACR &= ~FLASH_ACR_LATENCY;
 8000206:	4a21      	ldr	r2, [pc, #132]	; (800028c <clock_init+0x98>)
 8000208:	6811      	ldr	r1, [r2, #0]
 800020a:	f021 0107 	bic.w	r1, r1, #7
 800020e:	6011      	str	r1, [r2, #0]
	FLASH->ACR |= FLASH_ACR_LATENCY_0;
 8000210:	6811      	ldr	r1, [r2, #0]
 8000212:	f041 0101 	orr.w	r1, r1, #1
 8000216:	6011      	str	r1, [r2, #0]
	FLASH->ACR |= FLASH_ACR_PRFTBE;
 8000218:	6811      	ldr	r1, [r2, #0]
 800021a:	f041 0110 	orr.w	r1, r1, #16
 800021e:	6011      	str	r1, [r2, #0]

	RCC->CFGR |= RCC_CFGR_PLLSRC;
 8000220:	685a      	ldr	r2, [r3, #4]
 8000222:	f442 3280 	orr.w	r2, r2, #65536	; 0x10000
 8000226:	605a      	str	r2, [r3, #4]
	RCC->CFGR |= RCC_CFGR_PLLMULL6;
 8000228:	685a      	ldr	r2, [r3, #4]
 800022a:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
 800022e:	605a      	str	r2, [r3, #4]

	RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
 8000230:	685a      	ldr	r2, [r3, #4]
 8000232:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
 8000236:	605a      	str	r2, [r3, #4]

	RCC->CR |= RCC_CR_PLLON;
 8000238:	681a      	ldr	r2, [r3, #0]
 800023a:	f042 7280 	orr.w	r2, r2, #16777216	; 0x1000000
 800023e:	601a      	str	r2, [r3, #0]
	while( !(RCC->CR & RCC_CR_PLLRDY) ){}
 8000240:	681a      	ldr	r2, [r3, #0]
 8000242:	0192      	lsls	r2, r2, #6
 8000244:	d5fc      	bpl.n	8000240 <clock_init+0x4c>

	RCC->CFGR |= RCC_CFGR_SW_PLL;
 8000246:	685a      	ldr	r2, [r3, #4]
 8000248:	f042 0202 	orr.w	r2, r2, #2
 800024c:	605a      	str	r2, [r3, #4]
	while( (RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08 ){}
 800024e:	685a      	ldr	r2, [r3, #4]
 8000250:	f002 020c 	and.w	r2, r2, #12
 8000254:	2a08      	cmp	r2, #8
 8000256:	d1fa      	bne.n	800024e <clock_init+0x5a>