fork(7) download
  1. #include <stdio.h>
  2. #include <stdint.h>
  3. #include <string.h>
  4. #include <stdbool.h>
  5.  
  6. static uint8_t code[] = {
  7. 0x00,0x02,0x87,0xe8,0x00,0x12,0xf8,0xfb,
  8. 0x00,0x22,0x49,0x37,0x00,0x32,0x1f,0x4e,
  9. 0x07,0x32,0x80,0x89,0x01,0x32,0x66,0x4c,
  10. 0x05,0xc3,0x05,0xf3,0x01,0x12,0x73,0xa9,
  11. 0x07,0x22,0x9b,0xe5,0x03,0x83,0x06,0x12,
  12. 0xb3,0xb6,0x05,0x02,0xa8,0x7b,0x05,0xf3,
  13. 0x00,0x32,0x0a,0x00,0x03,0x93,0x03,0x22,
  14. 0x69,0x76,0x04,0x01,0x0b,0x31,0x0f,0x00,
  15. 0x10,0x00,0x05,0x12,0xb4,0x36,0x00,0xc3,
  16. 0x07,0x02,0x07,0x35,0x03,0x83,0x05,0x12,
  17. 0x0f,0x64,0x00,0x43,0x03,0xb3,0x08,0x02,
  18. 0x02,0x00,0x05,0x23,0x01,0xb3,0x07,0xc3,
  19. 0x05,0x02,0x5e,0xd6,0x07,0x83,0x06,0x73,
  20. 0x02,0x32,0x80,0x14,0x03,0x12,0x7b,0x4b,
  21. 0x06,0x12,0xa1,0x28,0x01,0x22,0x17,0x30,
  22. 0x02,0xa3,0x00,0x12,0x6d,0xda,0x01,0x53,
  23. 0x02,0x23,0x04,0x11,0x03,0x03,0x07,0x02,
  24. 0x17,0x04,0x03,0xc3,0x03,0x12,0x4b,0xac,
  25. 0x02,0x32,0xce,0x33,0x01,0x03,0x06,0x12,
  26. 0x12,0x8e,
  27. };
  28.  
  29. static const char *op_names[] = {
  30. "MOVE", "OR", "XOR", "AND", "NOT", "ADD", "SUB", "MUL", "SHL", "SHR",
  31. "INC", "DEC", "PUSH", "POP", "CMP", "JNZ", "JZ",
  32. };
  33.  
  34. typedef struct instruction {
  35. size_t offset;
  36. unsigned int opcode;
  37. unsigned int mode;
  38. unsigned int rdest;
  39. unsigned int rsrc;
  40. uint16_t imm;
  41. } instruction;
  42.  
  43.  
  44. int main(void)
  45. {
  46. static instruction instructions[16384];
  47. size_t num_instructions = 0;
  48.  
  49. for (size_t i = 0; i < sizeof(code); i += 2) {
  50. unsigned int opt = code[i + 1];
  51.  
  52. instruction insn = {
  53. .offset = i,
  54. .opcode = code[i],
  55. .mode = opt & 15,
  56. .rdest = (opt >> 4) & 3,
  57. .rsrc = (opt >> 6) & 3,
  58. .imm = 0xbaadU,
  59. };
  60.  
  61. if (insn.opcode >= sizeof(op_names) / sizeof(op_names[0])) {
  62. fprintf(stderr, "Wrong opcode %u at %.8zx\n", insn.opcode, insn.offset);
  63. return 1;
  64. }
  65.  
  66. if (insn.mode >= 4) {
  67. fprintf(stderr, "Wrong mode %u at %.8zx\n", insn.mode, insn.offset);
  68. return 1;
  69. }
  70.  
  71. if (insn.mode == 0 || insn.mode == 2) {
  72. i += 2;
  73. insn.imm = code[i] | code[i + 1] << 8;
  74. }
  75. instructions[num_instructions++] = insn;
  76. }
  77.  
  78. size_t ip = 0;
  79. uint16_t regs[4] = { 0 };
  80. uint16_t stack[256];
  81. size_t stackptr = 0;
  82. bool zf = false;
  83.  
  84. while (ip < num_instructions) {
  85. instruction *insn = &instructions[ip];
  86. uint16_t *dest = NULL;
  87. uint16_t *src = NULL;
  88. uint16_t imm = insn->imm;
  89.  
  90. printf("%.4zx: %s\t", ip, op_names[insn->opcode]);
  91.  
  92. switch (insn->mode) {
  93. case 0: // IMM.
  94. dest = &imm;
  95. printf("%.4x\t", insn->imm);
  96. break;
  97. case 1: // REG.
  98. dest = &regs[insn->rdest];
  99. printf("r%u\t", insn->rdest);
  100. break;
  101. case 2: // REG, IMM.
  102. dest = &regs[insn->rdest];
  103. src = &imm;
  104. printf("r%u, %.4x", insn->rdest, insn->imm);
  105. break;
  106. case 3: // REG, REG.
  107. dest = &regs[insn->rdest];
  108. src = &regs[insn->rsrc];
  109. printf("r%u, r%u\t", insn->rdest, insn->rsrc);
  110. break;
  111. }
  112.  
  113. printf(" ; ");
  114. ++ip;
  115.  
  116. switch (insn->opcode) {
  117. case 0: // MOVE.
  118. *dest = *src;
  119. break;
  120. case 1: // OR.
  121. *dest = *dest || *src;
  122. break;
  123. case 2: // XOR.
  124. *dest = (*dest || *src) && !(*dest && *src);
  125. break;
  126. case 3: // AND.
  127. *dest = *dest && *src;
  128. break;
  129. case 4: // NOT.
  130. *dest = !*dest;
  131. break;
  132. case 5: // ADD.
  133. *dest += *src;
  134. break;
  135. case 6: // SUB.
  136. *dest -= *src;
  137. break;
  138. case 7: // MUL.
  139. *dest *= *src;
  140. break;
  141. case 8: // SHL.
  142. *dest <<= *src;
  143. break;
  144. case 9: // SHR.
  145. *dest >>= *src;
  146. break;
  147. case 10: // INC.
  148. *dest += 1;
  149. break;
  150. case 11: // DEC.
  151. *dest -= 1;
  152. break;
  153. case 12: // PUSH.
  154. if (stackptr >= sizeof(stack) / sizeof(stack[0])) {
  155. fprintf(stderr, "Stack overflow\n");
  156. return 2;
  157. }
  158. stack[stackptr++] = *dest;
  159. break;
  160. case 13: // POP
  161. if (stackptr == 0) {
  162. fprintf(stderr, "Stack underflow\n");
  163. return 2;
  164. }
  165. *dest = stack[--stackptr];
  166. break;
  167. case 14: // CMP.
  168. zf = (*dest - *src) == 0;
  169. break;
  170. case 15: // JNZ.
  171. if (!zf) {
  172. ip = *dest;
  173. }
  174. break;
  175. case 16: // JZ.
  176. if (zf) {
  177. ip = *dest;
  178. }
  179. break;
  180. }
  181.  
  182. if (insn->opcode >= 1 && insn->opcode <= 11) {
  183. zf = *dest == 0;
  184. }
  185.  
  186. printf(" r0 = %.4x, r1 = %.4x, r2 = %.4x, r3 = %.4x, zf = %u\n",
  187. regs[0], regs[1], regs[2], regs[3], zf);
  188. }
  189. }
  190.  
Success #stdin #stdout 0s 10832KB
stdin
Standard input is empty
stdout
0000: MOVE	r0, e887 ;  r0 = e887, r1 = 0000, r2 = 0000, r3 = 0000, zf = 0
0001: MOVE	r1, fbf8 ;  r0 = e887, r1 = fbf8, r2 = 0000, r3 = 0000, zf = 0
0002: MOVE	r2, 3749 ;  r0 = e887, r1 = fbf8, r2 = 3749, r3 = 0000, zf = 0
0003: MOVE	r3, 4e1f ;  r0 = e887, r1 = fbf8, r2 = 3749, r3 = 4e1f, zf = 0
0004: MUL	r3, 8980 ;  r0 = e887, r1 = fbf8, r2 = 3749, r3 = a680, zf = 0
0005: OR	r3, 4c66 ;  r0 = e887, r1 = fbf8, r2 = 3749, r3 = 0001, zf = 0
0006: ADD	r0, r3	 ;  r0 = e888, r1 = fbf8, r2 = 3749, r3 = 0001, zf = 0
0007: ADD	r3, r3	 ;  r0 = e888, r1 = fbf8, r2 = 3749, r3 = 0002, zf = 0
0008: OR	r1, a973 ;  r0 = e888, r1 = 0001, r2 = 3749, r3 = 0002, zf = 0
0009: MUL	r2, e59b ;  r0 = e888, r1 = 0001, r2 = c633, r3 = 0002, zf = 0
000a: AND	r0, r2	 ;  r0 = 0001, r1 = 0001, r2 = c633, r3 = 0002, zf = 0
000b: SUB	r1, b6b3 ;  r0 = 0001, r1 = 494e, r2 = c633, r3 = 0002, zf = 0
000c: ADD	r0, 7ba8 ;  r0 = 7ba9, r1 = 494e, r2 = c633, r3 = 0002, zf = 0
000d: ADD	r3, r3	 ;  r0 = 7ba9, r1 = 494e, r2 = c633, r3 = 0004, zf = 0
000e: MOVE	r3, 000a ;  r0 = 7ba9, r1 = 494e, r2 = c633, r3 = 000a, zf = 0
000f: AND	r1, r2	 ;  r0 = 7ba9, r1 = 0001, r2 = c633, r3 = 000a, zf = 0
0010: AND	r2, 7669 ;  r0 = 7ba9, r1 = 0001, r2 = 0001, r3 = 000a, zf = 0
0011: NOT	r0	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 000a, zf = 1
0012: DEC	r3	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0009, zf = 0
0013: JNZ	0010	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0009, zf = 0
0010: AND	r2, 7669 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0009, zf = 0
0011: NOT	r0	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0009, zf = 0
0012: DEC	r3	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0008, zf = 0
0013: JNZ	0010	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0008, zf = 0
0010: AND	r2, 7669 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0008, zf = 0
0011: NOT	r0	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0008, zf = 1
0012: DEC	r3	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0007, zf = 0
0013: JNZ	0010	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0007, zf = 0
0010: AND	r2, 7669 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0007, zf = 0
0011: NOT	r0	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0007, zf = 0
0012: DEC	r3	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0006, zf = 0
0013: JNZ	0010	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0006, zf = 0
0010: AND	r2, 7669 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0006, zf = 0
0011: NOT	r0	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0006, zf = 1
0012: DEC	r3	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0005, zf = 0
0013: JNZ	0010	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0005, zf = 0
0010: AND	r2, 7669 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0005, zf = 0
0011: NOT	r0	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0005, zf = 0
0012: DEC	r3	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0004, zf = 0
0013: JNZ	0010	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0004, zf = 0
0010: AND	r2, 7669 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0004, zf = 0
0011: NOT	r0	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0004, zf = 1
0012: DEC	r3	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0003, zf = 0
0013: JNZ	0010	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0003, zf = 0
0010: AND	r2, 7669 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0003, zf = 0
0011: NOT	r0	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0003, zf = 0
0012: DEC	r3	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0002, zf = 0
0013: JNZ	0010	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0002, zf = 0
0010: AND	r2, 7669 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0002, zf = 0
0011: NOT	r0	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0002, zf = 1
0012: DEC	r3	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0001, zf = 0
0013: JNZ	0010	 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0001, zf = 0
0010: AND	r2, 7669 ;  r0 = 0000, r1 = 0001, r2 = 0001, r3 = 0001, zf = 0
0011: NOT	r0	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0001, zf = 0
0012: DEC	r3	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0000, zf = 1
0013: JNZ	0010	 ;  r0 = 0001, r1 = 0001, r2 = 0001, r3 = 0000, zf = 1
0014: ADD	r1, 36b4 ;  r0 = 0001, r1 = 36b5, r2 = 0001, r3 = 0000, zf = 0
0015: MOVE	r0, r3	 ;  r0 = 0000, r1 = 36b5, r2 = 0001, r3 = 0000, zf = 0
0016: MUL	r0, 3507 ;  r0 = 0000, r1 = 36b5, r2 = 0001, r3 = 0000, zf = 1
0017: AND	r0, r2	 ;  r0 = 0000, r1 = 36b5, r2 = 0001, r3 = 0000, zf = 1
0018: ADD	r1, 640f ;  r0 = 0000, r1 = 9ac4, r2 = 0001, r3 = 0000, zf = 0
0019: MOVE	r0, r1	 ;  r0 = 9ac4, r1 = 9ac4, r2 = 0001, r3 = 0000, zf = 0
001a: AND	r3, r2	 ;  r0 = 9ac4, r1 = 9ac4, r2 = 0001, r3 = 0000, zf = 1
001b: SHL	r0, 0002 ;  r0 = 6b10, r1 = 9ac4, r2 = 0001, r3 = 0000, zf = 0
001c: ADD	r2, r0	 ;  r0 = 6b10, r1 = 9ac4, r2 = 6b11, r3 = 0000, zf = 0
001d: OR	r3, r2	 ;  r0 = 6b10, r1 = 9ac4, r2 = 6b11, r3 = 0001, zf = 0
001e: MUL	r0, r3	 ;  r0 = 6b10, r1 = 9ac4, r2 = 6b11, r3 = 0001, zf = 0
001f: ADD	r0, d65e ;  r0 = 416e, r1 = 9ac4, r2 = 6b11, r3 = 0001, zf = 0
0020: MUL	r0, r2	 ;  r0 = 524e, r1 = 9ac4, r2 = 6b11, r3 = 0001, zf = 0
0021: SUB	r3, r1	 ;  r0 = 524e, r1 = 9ac4, r2 = 6b11, r3 = 653d, zf = 0
0022: XOR	r3, 1480 ;  r0 = 524e, r1 = 9ac4, r2 = 6b11, r3 = 0000, zf = 1
0023: AND	r1, 4b7b ;  r0 = 524e, r1 = 0001, r2 = 6b11, r3 = 0000, zf = 0
0024: SUB	r1, 28a1 ;  r0 = 524e, r1 = d760, r2 = 6b11, r3 = 0000, zf = 0
0025: OR	r2, 3017 ;  r0 = 524e, r1 = d760, r2 = 0001, r3 = 0000, zf = 0
0026: XOR	r2, r2	 ;  r0 = 524e, r1 = d760, r2 = 0000, r3 = 0000, zf = 1
0027: MOVE	r1, da6d ;  r0 = 524e, r1 = da6d, r2 = 0000, r3 = 0000, zf = 1
0028: OR	r1, r1	 ;  r0 = 524e, r1 = 0001, r2 = 0000, r3 = 0000, zf = 0
0029: XOR	r2, r0	 ;  r0 = 524e, r1 = 0001, r2 = 0001, r3 = 0000, zf = 0
002a: NOT	r1	 ;  r0 = 524e, r1 = 0000, r2 = 0001, r3 = 0000, zf = 1
002b: AND	r0, r0	 ;  r0 = 0001, r1 = 0000, r2 = 0001, r3 = 0000, zf = 0
002c: MUL	r0, 0417 ;  r0 = 0417, r1 = 0000, r2 = 0001, r3 = 0000, zf = 0
002d: AND	r0, r3	 ;  r0 = 0000, r1 = 0000, r2 = 0001, r3 = 0000, zf = 1
002e: AND	r1, ac4b ;  r0 = 0000, r1 = 0000, r2 = 0001, r3 = 0000, zf = 1
002f: XOR	r3, 33ce ;  r0 = 0000, r1 = 0000, r2 = 0001, r3 = 0001, zf = 0
0030: OR	r0, r0	 ;  r0 = 0000, r1 = 0000, r2 = 0001, r3 = 0001, zf = 1
0031: SUB	r1, 8e12 ;  r0 = 0000, r1 = 71ee, r2 = 0001, r3 = 0001, zf = 0