#define DIVIDE_ITER_0_0(i) \
" lsl %D[n]\n" \
" rol %A[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" or %D[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_1_6(i) \
" lsl %D[n]\n" \
" rol %A[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" or %D[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_7_7(i) \
" lsl %D[n]\n" \
" rol %A[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" or %D[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" mov __tmp_reg__,%A[q]\n"
#define DIVIDE_ITER_8_8(i) \
" lsl %C[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" or %C[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_9_14(i) \
" lsl %C[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" or %C[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_15_15(i) \
" lsl %C[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" or %C[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" mov __tmp_reg__,%A[q]\n"
#define DIVIDE_ITER_16_16(i) \
" lsl %B[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" rol %C[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" or %B[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_17_22(i) \
" lsl %B[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" rol %C[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" sbc %C[p],%C[d]\n" \
" or %B[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_23_23(i) \
" lsl %B[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" rol %C[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" sbc %C[p],%C[d]\n" \
" or %B[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" mov __tmp_reg__,%A[q]\n" \
" clr %A[q]\n"
#define DIVIDE_ITER_24_24(i) \
" lsl %A[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" rol %C[p]\n" \
" rol %D[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" sbc %C[p],%C[d]\n" \
" or %A[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_25_29(i) \
" lsl %A[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" rol %C[p]\n" \
" rol %D[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" sbc %C[p],%C[d]\n" \
" sbc %D[p],%D[d]\n" \
" or %A[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_30_30(i) \
" lsl %A[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" rol %C[p]\n" \
" rol %D[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" sbc %C[p],%C[d]\n" \
" sbc %D[p],%D[d]\n" \
" or %A[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
static uint32_t div32 (uint32_t n, uint32_t d)
{
uint32_t p = 0;
uint32_t q = 0x80;
asm(
" mov __tmp_reg__,%A[q]\n"
DIVIDE_ITER_0_0(0)
DIVIDE_ITER_1_6(1)
DIVIDE_ITER_1_6(2)
DIVIDE_ITER_1_6(3)
DIVIDE_ITER_1_6(4)
DIVIDE_ITER_1_6(5)
DIVIDE_ITER_1_6(6)
DIVIDE_ITER_7_7(7)
DIVIDE_ITER_8_8(8)
DIVIDE_ITER_9_14(9)
DIVIDE_ITER_9_14(10)
DIVIDE_ITER_9_14(11)
DIVIDE_ITER_9_14(12)
DIVIDE_ITER_9_14(13)
DIVIDE_ITER_9_14(14)
DIVIDE_ITER_15_15(15)
DIVIDE_ITER_16_16(16)
DIVIDE_ITER_17_22(17)
DIVIDE_ITER_17_22(18)
DIVIDE_ITER_17_22(19)
DIVIDE_ITER_17_22(20)
DIVIDE_ITER_17_22(21)
DIVIDE_ITER_17_22(22)
DIVIDE_ITER_23_23(23)
DIVIDE_ITER_24_24(24)
DIVIDE_ITER_25_29(25)
DIVIDE_ITER_25_29(26)
DIVIDE_ITER_25_29(27)
DIVIDE_ITER_25_29(28)
DIVIDE_ITER_25_29(29)
DIVIDE_ITER_30_30(30)
" lsl %A[n]\n"
" rol %A[p]\n"
" rol %B[p]\n"
" rol %C[p]\n"
" rol %D[p]\n"
" cp %A[p],%A[d]\n"
" cpc %B[p],%B[d]\n"
" cpc %C[p],%C[d]\n"
" cpc %D[p],%D[d]\n"
" brcs end_zero_bit%=\n"
" inc %A[q]\n"
"end_zero_bit%=:\n"
: [p] "=&r" (p),
[q] "=&r" (q),
[n] "=&r" (n)
: "[p]" (p),
"[q]" (q),
"[n]" (n),
[d] "r" (d)
);
return q;
}
#define DIVIDE_ITER_0_0(i) \
"    lsl %D[n]\n" \
"    rol %A[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    or %D[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    lsr __tmp_reg__\n"

#define DIVIDE_ITER_1_6(i) \
"    lsl %D[n]\n" \
"    rol %A[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    or %D[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    lsr __tmp_reg__\n"

#define DIVIDE_ITER_7_7(i) \
"    lsl %D[n]\n" \
"    rol %A[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    or %D[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    mov __tmp_reg__,%A[q]\n"

#define DIVIDE_ITER_8_8(i) \
"    lsl %C[n]\n" \
"    rol %A[p]\n" \
"    rol %B[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    or %C[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    lsr __tmp_reg__\n"

#define DIVIDE_ITER_9_14(i) \
"    lsl %C[n]\n" \
"    rol %A[p]\n" \
"    rol %B[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    sbc %B[p],%B[d]\n" \
"    or %C[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    lsr __tmp_reg__\n"

#define DIVIDE_ITER_15_15(i) \
"    lsl %C[n]\n" \
"    rol %A[p]\n" \
"    rol %B[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    sbc %B[p],%B[d]\n" \
"    or %C[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    mov __tmp_reg__,%A[q]\n"

#define DIVIDE_ITER_16_16(i) \
"    lsl %B[n]\n" \
"    rol %A[p]\n" \
"    rol %B[p]\n" \
"    rol %C[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    sbc %B[p],%B[d]\n" \
"    or %B[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    lsr __tmp_reg__\n"

#define DIVIDE_ITER_17_22(i) \
"    lsl %B[n]\n" \
"    rol %A[p]\n" \
"    rol %B[p]\n" \
"    rol %C[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    sbc %B[p],%B[d]\n" \
"    sbc %C[p],%C[d]\n" \
"    or %B[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    lsr __tmp_reg__\n"

#define DIVIDE_ITER_23_23(i) \
"    lsl %B[n]\n" \
"    rol %A[p]\n" \
"    rol %B[p]\n" \
"    rol %C[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    sbc %B[p],%B[d]\n" \
"    sbc %C[p],%C[d]\n" \
"    or %B[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    mov __tmp_reg__,%A[q]\n" \
"    clr %A[q]\n"

#define DIVIDE_ITER_24_24(i) \
"    lsl %A[n]\n" \
"    rol %A[p]\n" \
"    rol %B[p]\n" \
"    rol %C[p]\n" \
"    rol %D[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    sbc %B[p],%B[d]\n" \
"    sbc %C[p],%C[d]\n" \
"    or %A[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    lsr __tmp_reg__\n"

#define DIVIDE_ITER_25_29(i) \
"    lsl %A[n]\n" \
"    rol %A[p]\n" \
"    rol %B[p]\n" \
"    rol %C[p]\n" \
"    rol %D[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    sbc %B[p],%B[d]\n" \
"    sbc %C[p],%C[d]\n" \
"    sbc %D[p],%D[d]\n" \
"    or %A[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
"    lsr __tmp_reg__\n"

#define DIVIDE_ITER_30_30(i) \
"    lsl %A[n]\n" \
"    rol %A[p]\n" \
"    rol %B[p]\n" \
"    rol %C[p]\n" \
"    rol %D[p]\n" \
"    cp %A[p],%A[d]\n" \
"    cpc %B[p],%B[d]\n" \
"    cpc %C[p],%C[d]\n" \
"    cpc %D[p],%D[d]\n" \
"    brcs zero_bit_" #i "_%=\n" \
"    sub %A[p],%A[d]\n" \
"    sbc %B[p],%B[d]\n" \
"    sbc %C[p],%C[d]\n" \
"    sbc %D[p],%D[d]\n" \
"    or %A[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \

static uint32_t div32 (uint32_t n, uint32_t d)
{
    uint32_t p = 0;
    uint32_t q = 0x80;
    
    asm(
        "    mov __tmp_reg__,%A[q]\n"
        DIVIDE_ITER_0_0(0)
        DIVIDE_ITER_1_6(1)
        DIVIDE_ITER_1_6(2)
        DIVIDE_ITER_1_6(3)
        DIVIDE_ITER_1_6(4)
        DIVIDE_ITER_1_6(5)
        DIVIDE_ITER_1_6(6)
        DIVIDE_ITER_7_7(7)
        DIVIDE_ITER_8_8(8)
        DIVIDE_ITER_9_14(9)
        DIVIDE_ITER_9_14(10)
        DIVIDE_ITER_9_14(11)
        DIVIDE_ITER_9_14(12)
        DIVIDE_ITER_9_14(13)
        DIVIDE_ITER_9_14(14)
        DIVIDE_ITER_15_15(15)
        DIVIDE_ITER_16_16(16)
        DIVIDE_ITER_17_22(17)
        DIVIDE_ITER_17_22(18)
        DIVIDE_ITER_17_22(19)
        DIVIDE_ITER_17_22(20)
        DIVIDE_ITER_17_22(21)
        DIVIDE_ITER_17_22(22)
        DIVIDE_ITER_23_23(23)
        DIVIDE_ITER_24_24(24)
        DIVIDE_ITER_25_29(25)
        DIVIDE_ITER_25_29(26)
        DIVIDE_ITER_25_29(27)
        DIVIDE_ITER_25_29(28)
        DIVIDE_ITER_25_29(29)
        DIVIDE_ITER_30_30(30)
        "    lsl %A[n]\n"
        "    rol %A[p]\n"
        "    rol %B[p]\n"
        "    rol %C[p]\n"
        "    rol %D[p]\n"
        "    cp %A[p],%A[d]\n"
        "    cpc %B[p],%B[d]\n"
        "    cpc %C[p],%C[d]\n"
        "    cpc %D[p],%D[d]\n"
        "    brcs end_zero_bit%=\n"
        "    inc %A[q]\n"
        "end_zero_bit%=:\n"
        
        : [p] "=&r" (p),
          [q] "=&r" (q),
          [n] "=&r" (n)
        : "[p]" (p),
          "[q]" (q),
          "[n]" (n),
          [d] "r" (d)
    );
    
    return q;
}