#define DIVIDE_ITER_0_6(i) \
" lsl %D[n]\n" \
" rol %A[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" or %D[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_7_7(i) \
" lsl %D[n]\n" \
" rol %A[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" or %D[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" mov __tmp_reg__,%A[q]\n"
#define DIVIDE_ITER_8_14(i) \
" lsl %C[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" or %C[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_15_15(i) \
" lsl %C[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" or %C[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" mov __tmp_reg__,%A[q]\n"
#define DIVIDE_ITER_16_22(i) \
" lsl %B[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" rol %C[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" sbc %C[p],%C[d]\n" \
" or %B[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_23_23(i) \
" lsl %B[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" rol %C[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" sbc %C[p],%C[d]\n" \
" or %B[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" mov __tmp_reg__,%A[q]\n" \
" clr %A[q]\n"
#define DIVIDE_ITER_24_29(i) \
" lsl %A[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" rol %C[p]\n" \
" rol %D[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" sbc %C[p],%C[d]\n" \
" sbc %D[p],%D[d]\n" \
" or %A[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
" lsr __tmp_reg__\n"
#define DIVIDE_ITER_30_30(i) \
" lsl %A[n]\n" \
" rol %A[p]\n" \
" rol %B[p]\n" \
" rol %C[p]\n" \
" rol %D[p]\n" \
" cp %A[p],%A[d]\n" \
" cpc %B[p],%B[d]\n" \
" cpc %C[p],%C[d]\n" \
" cpc %D[p],%D[d]\n" \
" brcs zero_bit_" #i "_%=\n" \
" sub %A[p],%A[d]\n" \
" sbc %B[p],%B[d]\n" \
" sbc %C[p],%C[d]\n" \
" sbc %D[p],%D[d]\n" \
" or %A[q],__tmp_reg__\n" \
"zero_bit_" #i "_%=:\n" \
static uint32_t div32 (uint32_t n, uint32_t d)
{
uint32_t p = 0;
uint32_t q = 0x80;
asm(
" mov __tmp_reg__,%A[q]\n"
DIVIDE_ITER_0_6(0)
DIVIDE_ITER_0_6(1)
DIVIDE_ITER_0_6(2)
DIVIDE_ITER_0_6(3)
DIVIDE_ITER_0_6(4)
DIVIDE_ITER_0_6(5)
DIVIDE_ITER_0_6(6)
DIVIDE_ITER_7_7(7)
DIVIDE_ITER_8_14(8)
DIVIDE_ITER_8_14(9)
DIVIDE_ITER_8_14(10)
DIVIDE_ITER_8_14(11)
DIVIDE_ITER_8_14(12)
DIVIDE_ITER_8_14(13)
DIVIDE_ITER_8_14(14)
DIVIDE_ITER_15_15(15)
DIVIDE_ITER_16_22(16)
DIVIDE_ITER_16_22(17)
DIVIDE_ITER_16_22(18)
DIVIDE_ITER_16_22(19)
DIVIDE_ITER_16_22(20)
DIVIDE_ITER_16_22(21)
DIVIDE_ITER_16_22(22)
DIVIDE_ITER_23_23(23)
DIVIDE_ITER_24_29(24)
DIVIDE_ITER_24_29(25)
DIVIDE_ITER_24_29(26)
DIVIDE_ITER_24_29(27)
DIVIDE_ITER_24_29(28)
DIVIDE_ITER_24_29(29)
DIVIDE_ITER_30_30(30)
" lsl %A[n]\n"
" rol %A[p]\n"
" rol %B[p]\n"
" rol %C[p]\n"
" rol %D[p]\n"
" cp %A[p],%A[d]\n"
" cpc %B[p],%B[d]\n"
" cpc %C[p],%C[d]\n"
" cpc %D[p],%D[d]\n"
" brcs end_zero_bit%=\n"
" inc %A[q]\n"
"end_zero_bit%=:\n"
: [p] "=&r" (p),
[q] "=&r" (q),
[n] "=&r" (n)
: "[p]" (p),
"[q]" (q),
"[n]" (n),
[d] "r" (d)
);
return q;
}
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VklERV9JVEVSXzE2XzIyKDE4KQogICAgICAgIERJVklERV9JVEVSXzE2XzIyKDE5KQogICAgICAgIERJVklERV9JVEVSXzE2XzIyKDIwKQogICAgICAgIERJVklERV9JVEVSXzE2XzIyKDIxKQogICAgICAgIERJVklERV9JVEVSXzE2XzIyKDIyKQogICAgICAgIERJVklERV9JVEVSXzIzXzIzKDIzKQogICAgICAgIERJVklERV9JVEVSXzI0XzI5KDI0KQogICAgICAgIERJVklERV9JVEVSXzI0XzI5KDI1KQogICAgICAgIERJVklERV9JVEVSXzI0XzI5KDI2KQogICAgICAgIERJVklERV9JVEVSXzI0XzI5KDI3KQogICAgICAgIERJVklERV9JVEVSXzI0XzI5KDI4KQogICAgICAgIERJVklERV9JVEVSXzI0XzI5KDI5KQogICAgICAgIERJVklERV9JVEVSXzMwXzMwKDMwKQogICAgICAgICIgICAgbHNsICVBW25dXG4iCiAgICAgICAgIiAgICByb2wgJUFbcF1cbiIKICAgICAgICAiICAgIHJvbCAlQltwXVxuIgogICAgICAgICIgICAgcm9sICVDW3BdXG4iCiAgICAgICAgIiAgICByb2wgJURbcF1cbiIKICAgICAgICAiICAgIGNwICVBW3BdLCVBW2RdXG4iCiAgICAgICAgIiAgICBjcGMgJUJbcF0sJUJbZF1cbiIKICAgICAgICAiICAgIGNwYyAlQ1twXSwlQ1tkXVxuIgogICAgICAgICIgICAgY3BjICVEW3BdLCVEW2RdXG4iCiAgICAgICAgIiAgICBicmNzIGVuZF96ZXJvX2JpdCU9XG4iCiAgICAgICAgIiAgICBpbmMgJUFbcV1cbiIKICAgICAgICAiZW5kX3plcm9fYml0JT06XG4iCiAgICAgICAgCiAgICAgICAgOiBbcF0gIj0mciIgKHApLAogICAgICAgICAgW3FdICI9JnIiIChxKSwKICAgICAgICAgIFtuXSAiPSZyIiAobikKICAgICAgICA6ICJbcF0iIChwKSwKICAgICAgICAgICJbcV0iIChxKSwKICAgICAgICAgICJbbl0iIChuKSwKICAgICAgICAgIFtkXSAiciIgKGQpCiAgICApOwogICAgCiAgICByZXR1cm4gcTsKfQ==