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  1. entity project4 is
  2.     Port ( clk : in  STD_LOGIC;
  3.            reset : in  STD_LOGIC;
  4.            x : in  STD_LOGIC_VECTOR (1 downto 0);
  5.            myoutputs : out  STD_LOGIC_VECTOR (2 downto 0));
  6. end project4;
  7.  
  8. architecture Behavioral of project4 is
  9. type state_type is (s0,s1,s2,s3,s4,s5,s6,s7);
  10. signal state: state_type;
  11.  
  12. begin
  13. process1: process(clk,reset)
  14. begin
  15.      if (reset ='0') THEN state <= s0;
  16. 	  myoutputs <= "000";
  17. ELSE IF (clk'EVENT AND clk='1') THEN
  18.     case state is
  19. 	 when s0 =>
  20. 	           if (x="00") THEN
  21. 				  state <= s1;
  22. 				  myoutputs <= "001";
  23. 				  ELSE IF (x="01") THEN
  24. 				  state <= s7;
  25. 				  myoutputs <= "111";
  26. 				  ELSE IF (x="10") THEN
  27. 				  state <= s2;
  28. 				  myoutputs <= "010";
  29. 				  ELSE
  30. 				  state <=s4;
  31. 				  myoutputs <= "100";
  32. 	  END IF;
  33.  
  34. 	  when s1 =>
  35. 	            if (x="00") THEN
  36. 					state <= s2;
  37. 					myoutputs <="010";
  38. 					ELSE IF (x ="01") THEN
  39. 					state <= s0;
  40. 					myoutputs <= "000";
  41. 					ELSE IF (x ="10") THEN
  42. 					state <=s0;
  43. 					myoutputs <= "000";
  44. 					ELSE
  45. 					state <= s0;
  46. 					myoutputs <="000";
  47. 		END IF;
  48.  
  49. 		when s2 =>
  50. 		          if (x="00") THEN
  51. 					 state <= s3;
  52. 					 myoutputs <="011";
  53. 					 ELSE IF (x="01") THEN
  54. 					 state <= s1;
  55. 					 myoutputs <="001";
  56. 					 ELSE IF (x="10") THEN
  57. 					 state <=s5;
  58. 					 myoutputs <="110";
  59. 					 ELSE
  60. 					 state <=s3;
  61. 					 myoutputs <="011";
  62. 		END IF;
  63.  
  64. 		when s3 =>
  65. 		          if (x="00") THEN
  66. 					 state <=s4;
  67. 					 myoutputs <="100";
  68. 					 ELSE IF (x="01") THEN
  69. 					 state <= s2;
  70. 					 myoutputs <="010";
  71. 					 ELSE IF (x="10") THEN
  72. 					 state <= s1;
  73. 					 myoutputs <= "001";
  74. 					 ELSE
  75. 					 state <=s1;
  76. 					 myoutputs <= "001";
  77. 		END IF;
  78.  
  79.       when s4 =>
  80.                 if (x="00") THEN
  81.                 state <=s5;
  82.                 myoutputs <="101";
  83. 					 ELSE IF (x="01") THEN
  84. 					 state <= s3;
  85. 					 myoutputs <="011";
  86. 					 ELSE IF (x="10") THEN
  87. 					 state <= s5;
  88. 					 myoutputs <="101";
  89. 					 ELSE
  90. 					 state <= s5;
  91. 					 myoutputs <="101";
  92. 		END IF;
  93.  
  94. 		when s5 =>
  95. 		          if (x="00") THEN
  96. 					 state <= s6;
  97. 					 myoutputs <="110";
  98. 					 ELSE IF (x="01") THEN
  99. 					 state <= s4;
  100. 					 myoutputs <= "100";
  101. 					 ELSE IF (x="10") THEN
  102. 					 state <= s7;
  103. 					 myoutputs <= "111";
  104. 					 ELSE
  105. 					 state <= s7;
  106. 					 myoutputs <= "111";
  107. 		END IF;
  108.  
  109. 		when s6 =>
  110. 		          if (x="00") THEN
  111. 					 state <= s7;
  112. 					 myoutputs <= "111";
  113. 					 ELSE IF (x="01") THEN
  114. 					 state <= s5;
  115. 					 myoutputs <="101";
  116. 					 ELSE IF (x="10") THEN
  117. 					 state <= s4;
  118. 					 myoutputs <="100";
  119. 					 ELSE
  120. 					 state <= s2;
  121. 					 myoutputs <="010";
  122. 		END IF;
  123.  
  124. 		when s7 =>
  125. 		          if (x="00") THEN
  126. 					 state <= s0;
  127. 					 myoutputs <="000";
  128. 					 ELSE IF (x="01") THEN
  129. 					 state <= s6;
  130. 					 myoutputs <="110";
  131. 					 ELSE IF (x="10") THEN
  132. 					 state <= s3;
  133. 					 myoutputs <="011";
  134. 					 ELSE
  135. 					 state <= s6;
  136. 					 myoutputs <= "110";
  137. 		END IF;
  138. 		end case;
  139. 		end process process1;
  140.  
  141. process2: process(state)
  142. begin
  143.       case state is
  144. 		when s0 => myoutputs <= "000";
  145. 		when s1 => myoutputs <= "001";
  146. 		when s2 => myoutputs <= "010";
  147. 		when s3 => myoutputs <= "011";
  148. 		when s4 => myoutputs <= "100";
  149. 		when s5 => myoutputs <= "101";
  150. 		when s6 => myoutputs <= "110";
  151. 		when s7 => myoutputs <= "111";
  152. 		end case;
  153. end process process2;
  154.  
  155. end Behavioral;
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https://ideone.com/cYRXed
VHDL project 4
language:
Text (text 6.10)
created:
8 years ago
visibility:
public

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