#include <avr/io.h> // register and port definitions

#define T 160 // (16MHz/1)/200 = 80kHz

int main(void) {
  GTCCR  = 0b10000011; // assert and hold reset
  
  TCCR0A = 0b00100011; // COM0A=off, COM0B=2, WGM0=7 (FastPWM 0..OCRA)
  TCCR0B = 0b00001001; // WGM0=7, CS0=CLK/1 (16MHz)
  TIMSK0 = 0b00000000; // disable interrupts
  OCR0A  = T-1;        // F = 16MHz/T
  OCR0B  = 0.50*T;     // duty = 50%
  TCNT0  = 0;          // reset counter (0deg)
  
  TCCR1A = 0b00100011; // COM1A=off, COM1B=2, WGM1=15 (FastPWM 0..OCRA)
  TCCR1B = 0b00011001; // WGM1=15, CS0=CLK/1 (16MHz)
  TCCR1C = 0b00000000; // no force output compare
  TIMSK1 = 0b00000000; // disable interrupts
  ICR1   = 0;          // input capture register (unused)
  OCR1A  = T-1;        // F = (16MHz/1)/T
  OCR1B  = 0.50*T;     // duty = 50%
  //TCNT1  = 0.75*T;     // reset counter (90deg) // WORKSN'T
  TCNT1  = -0.25*T;    // reset counter (90deg) // WORKS
  
  TCCR2A = 0b00100011; // COM2A=off, COM2B=2, WGM2=7 (FastPWM 0..OCRA)
  TCCR2B = 0b00001001; // WGM2=7, CS2=CLK/1 (16MHz)
  TIMSK2 = 0b00000000; // disable interrupts
  OCR2A  = T-1;        // F = (16MHz/1)/T
  OCR2B  = 0.50*T;     // duty = 50%
  //TCNT2  = 0.50*T;     // reset counter (180deg) // WORKSN'T
  TCNT2  = -0.50*T;    // WORKS
  ASSR   = 0b00000000; // Clear async status reg

  DDRD   = 0b00101000; // PD5 (OC0B) = out, PD3 (OC2B) = out, PD6 (OC0A) = in
  DDRB   = 0b00000100; // PB2 (OC1B) = out, PB1 (OC1A) = in,  PB3 (OC2A) = in
  
  GTCCR  = 0b00000011; // release reset (will be auto-deasserted)
  
  return 0;
}

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