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  1. ----------------------------------------------------------------------------------
  2. -- Company: 
  3. -- Engineer:     	Mr.DDDAlKilanny
  4. -- 
  5. -- Create Date:    16:29:19 03/22/2013 
  6. -- Design Name: 
  7. -- Module Name:    RegisterFile - Behavioral 
  8. -- Project Name: 
  9. -- Target Devices: 
  10. -- Tool versions: 
  11. -- Description: 
  12. --
  13. -- Dependencies: 
  14. --
  15. -- Revision: 
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments: 
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. use work.mine.all;
  23.  
  24. -- Uncomment the following library declaration if using
  25. -- arithmetic functions with Signed or Unsigned values
  26. --use IEEE.NUMERIC_STD.ALL;
  27.  
  28. -- Uncomment the following library declaration if instantiating
  29. -- any Xilinx primitives in this code.
  30. --library UNISIM;
  31. --use UNISIM.VComponents.all;
  32.  
  33. entity RegisterFile is
  34. 	port (
  35. 		-- selector of mux1
  36. 		read_sel1 : in std_logic_vector(4 downto 0);
  37. 		-- selector of mux2
  38. 		read_sel2 : in std_logic_vector(4 downto 0);
  39. 		-- selector for destination register to write into
  40. 		write_sel : in std_logic_vector(4 downto 0);
  41. 		-- the write-enable for registers
  42. 		write_ena : in std_logic;
  43. 		-- the clock
  44. 		clk: in std_logic;
  45. 		-- the write data for destination register
  46. 		write_data: in std_logic_vector(31 downto 0);
  47. 		-- the output of mux1
  48. 		data1: out std_logic_vector(31 downto 0);
  49. 		-- the output of mux2
  50. 		data2: out std_logic_vector(31 downto 0)
  51. 	);
  52. end RegisterFile;
  53.  
  54. architecture Behavioral of RegisterFile is
  55. 	signal decout,
  56. 			reg1out, reg2out, reg3out, reg4out, reg5out,
  57. 			reg6out, reg7out, reg8out, reg9out, reg10out, reg11out,
  58. 			reg12out, reg13out, reg14out, reg15out, reg16out, reg17out,
  59. 			reg18out, reg19out, reg20out, reg21out, reg22out, reg23out,
  60. 			reg24out, reg25out, reg26out, reg27out, reg28out, reg29out,
  61. 			reg30out, reg31out, reg32out : std_logic_vector (31 downto 0);
  62. 	signal canwrite1, canwrite2, canwrite3, canwrite4, canwrite5,
  63. 			canwrite6, canwrite7, canwrite8, canwrite9, canwrite10,
  64. 			canwrite11, canwrite12, canwrite13, canwrite14, canwrite15,
  65. 			canwrite16, canwrite17, canwrite18, canwrite19, canwrite20,
  66. 			canwrite21, canwrite22, canwrite23, canwrite24, canwrite25,
  67. 			canwrite26, canwrite27, canwrite28, canwrite29, canwrite30,
  68. 			canwrite31, canwrite32 : std_logic;
  69. begin
  70. 	-- selects which register to write into
  71. 		-- in, enable, out
  72. 	D : dec port map (write_sel, '1', decout);
  73.  
  74. 		-- in_data, out_data, clk, write_ena, inc, clr
  75. 	R1 : reg port map (write_data, reg1out, clk, canwrite1, '0', '0');
  76. 	R2 : reg port map (write_data, reg2out, clk, canwrite2, '0', '0');
  77. 	R3 : reg port map (write_data, reg3out, clk, canwrite3, '0', '0');
  78. 	R4 : reg port map (write_data, reg4out, clk, canwrite4, '0', '0');
  79. 	R5 : reg port map (write_data, reg5out, clk, canwrite5, '0', '0');
  80. 	R6 : reg port map (write_data, reg6out, clk, canwrite6, '0', '0');
  81. 	R7 : reg port map (write_data, reg7out, clk, canwrite7, '0', '0');
  82. 	R8 : reg port map (write_data, reg8out, clk, canwrite8, '0', '0');
  83. 	R9 : reg port map (write_data, reg9out, clk, canwrite9, '0', '0');
  84. 	R10 : reg port map (write_data, reg10out, clk, canwrite10, '0', '0');
  85. 	R11 : reg port map (write_data, reg11out, clk, canwrite11, '0', '0');
  86. 	R12 : reg port map (write_data, reg12out, clk, canwrite12, '0', '0');
  87. 	R13 : reg port map (write_data, reg13out, clk, canwrite13, '0', '0');
  88. 	R14 : reg port map (write_data, reg14out, clk, canwrite14, '0', '0');
  89. 	R15 : reg port map (write_data, reg15out, clk, canwrite15, '0', '0');
  90. 	R16 : reg port map (write_data, reg16out, clk, canwrite16, '0', '0');
  91. 	R17 : reg port map (write_data, reg17out, clk, canwrite17, '0', '0');
  92. 	R18 : reg port map (write_data, reg18out, clk, canwrite18, '0', '0');
  93. 	R19 : reg port map (write_data, reg19out, clk, canwrite19, '0', '0');
  94. 	R20 : reg port map (write_data, reg20out, clk, canwrite20, '0', '0');
  95. 	R21 : reg port map (write_data, reg21out, clk, canwrite21, '0', '0');
  96. 	R22 : reg port map (write_data, reg22out, clk, canwrite22, '0', '0');
  97. 	R23 : reg port map (write_data, reg23out, clk, canwrite23, '0', '0');
  98. 	R24 : reg port map (write_data, reg24out, clk, canwrite24, '0', '0');
  99. 	R25 : reg port map (write_data, reg25out, clk, canwrite25, '0', '0');
  100. 	R26 : reg port map (write_data, reg26out, clk, canwrite26, '0', '0');
  101. 	R27 : reg port map (write_data, reg27out, clk, canwrite27, '0', '0');
  102. 	R28 : reg port map (write_data, reg28out, clk, canwrite28, '0', '0');
  103. 	R29 : reg port map (write_data, reg29out, clk, canwrite29, '0', '0');
  104. 	R30 : reg port map (write_data, reg30out, clk, canwrite30, '0', '0');
  105. 	R31 : reg port map (write_data, reg31out, clk, canwrite31, '0', '0');
  106. 	R32 : reg port map (write_data, reg32out, clk, canwrite32, '0', '0');
  107.  
  108. 	-- selects which register to read from	
  109. 	-- 		I0, I1, ..., I30, I31, selector, output, enable
  110. 	M1 : mux port map (reg1out, reg2out, reg3out, reg4out, reg5out,
  111. 			reg6out, reg7out, reg8out, reg9out, reg10out, reg11out,
  112. 			reg12out, reg13out, reg14out, reg15out, reg16out, reg17out,
  113. 			reg18out, reg19out, reg20out, reg21out, reg22out, reg23out,
  114. 			reg24out, reg25out, reg26out, reg27out, reg28out, reg29out,
  115. 			reg30out, reg31out, reg32out,
  116. 			read_sel1, data1, '1');
  117. 	M2 : mux port map (reg1out, reg2out, reg3out, reg4out, reg5out,
  118. 			reg6out, reg7out, reg8out, reg9out, reg10out, reg11out,
  119. 			reg12out, reg13out, reg14out, reg15out, reg16out, reg17out,
  120. 			reg18out, reg19out, reg20out, reg21out, reg22out, reg23out,
  121. 			reg24out, reg25out, reg26out, reg27out, reg28out, reg29out,
  122. 			reg30out, reg31out, reg32out,
  123. 			read_sel2, data2, '1');
  124.  
  125. 	process (clk)
  126. 	begin
  127. 		if (clk'event and clk = '0') then
  128. 			canwrite1 <= write_ena and decout(0);
  129. 			canwrite2 <= write_ena and decout(1);
  130. 			canwrite3 <= write_ena and decout(2);
  131. 			canwrite4 <= write_ena and decout(3);
  132. 			canwrite5 <= write_ena and decout(4);
  133. 			canwrite6 <= write_ena and decout(5);
  134. 			canwrite7 <= write_ena and decout(6);
  135. 			canwrite8 <= write_ena and decout(7);
  136. 			canwrite9 <= write_ena and decout(8);
  137. 			canwrite10 <= write_ena and decout(9);
  138. 			canwrite11 <= write_ena and decout(10);
  139. 			canwrite12 <= write_ena and decout(11);
  140. 			canwrite13 <= write_ena and decout(12);
  141. 			canwrite14 <= write_ena and decout(13);
  142. 			canwrite15 <= write_ena and decout(14);
  143. 			canwrite16 <= write_ena and decout(15);
  144. 			canwrite17 <= write_ena and decout(16);
  145. 			canwrite18 <= write_ena and decout(17);
  146. 			canwrite19 <= write_ena and decout(18);
  147. 			canwrite20 <= write_ena and decout(19);
  148. 			canwrite21 <= write_ena and decout(20);
  149. 			canwrite22 <= write_ena and decout(21);
  150. 			canwrite23 <= write_ena and decout(22);
  151. 			canwrite24 <= write_ena and decout(23);
  152. 			canwrite25 <= write_ena and decout(24);
  153. 			canwrite26 <= write_ena and decout(25);
  154. 			canwrite27 <= write_ena and decout(26);
  155. 			canwrite28 <= write_ena and decout(27);
  156. 			canwrite29 <= write_ena and decout(28);
  157. 			canwrite30 <= write_ena and decout(29);
  158. 			canwrite31 <= write_ena and decout(30);
  159. 			canwrite32 <= write_ena and decout(31);
  160. 		end if;
  161. 	end process;
  162.  
  163. end Behavioral;
  164.  
  165.  
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https://ideone.com/Rq9PqB
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