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  1. /* bcm2835.h
  2.  
  3.   C and C++ support for Broadcom BCM 2835 as used in Raspberry Pi
  4.  
  5.   Author: Mike McCauley
  6.   Copyright (C) 2011-2013 Mike McCauley
  7.   $Id: bcm2835.h,v 1.18 2015/03/08 22:17:20 mikem Exp $
  8. */
  9.  
  10. /*! \mainpage C library for Broadcom BCM 2835 as used in Raspberry Pi
  11.  
  12.   This is a C library for Raspberry Pi (RPi). It provides access to
  13.   GPIO and other IO functions on the Broadcom BCM 2835 chip,
  14.   allowing access to the GPIO pins on the
  15.   26 pin IDE plug on the RPi board so you can control and interface with various external devices.
  16.  
  17.   It provides functions for reading digital inputs and setting digital outputs, using SPI and I2C,
  18.   and for accessing the system timers.
  19.   Pin event detection is supported by polling (interrupts are not supported).
  20.  
  21.   It is C++ compatible, and installs as a header file and non-shared library on
  22.   any Linux-based distro (but clearly is no use except on Raspberry Pi or another board with
  23.   BCM 2835).
  24.  
  25.   The version of the package that this documentation refers to can be downloaded
  26.   from http: www.airspayce.com/mikem/bcm2835/bcm2835-1.42.tar.gz
  27.   You can find the latest version at http://w...content-available-to-author-only...e.com/mikem/bcm2835
  28.  
  29.   Several example programs are provided.
  30.  
  31.   Based on data in http://e...content-available-to-author-only...x.org/RPi_Low-level_peripherals and
  32.   http://w...content-available-to-author-only...i.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
  33.   and http://w...content-available-to-author-only...d.com/doc/101830961/GPIO-Pads-Control2
  34.  
  35.   You can also find online help and discussion at http://groups.google.com/group/bcm2835
  36.   Please use that group for all questions and discussions on this topic.
  37.   Do not contact the author directly, unless it is to discuss commercial licensing.
  38.   Before asking a question or reporting a bug, please read http://w...content-available-to-author-only...b.org/esr/faqs/smart-questions.html
  39.  
  40.   Tested on debian6-19-04-2012, 2012-07-15-wheezy-raspbian, 2013-07-26-wheezy-raspbian
  41.   and Occidentalisv01
  42.   CAUTION: it has been observed that when detect enables such as bcm2835_gpio_len()
  43.   are used and the pin is pulled LOW
  44.   it can cause temporary hangs on 2012-07-15-wheezy-raspbian, 2013-07-26-wheezy-raspbian
  45.   and Occidentalisv01.
  46.   Reason for this is not yet determined, but we suspect that an interrupt handler is
  47.   hitting a hard loop on those OSs.
  48.   If you must use bcm2835_gpio_len() and friends, make sure you disable the pins with
  49.   bcm2835_gpio_clr_len() and friends after use.
  50.  
  51.   \par Installation
  52.  
  53.   This library consists of a single non-shared library and header file, which will be
  54.   installed in the usual places by make install
  55.  
  56.   \code
  57.   # download the latest version of the library, say bcm2835-1.xx.tar.gz, then:
  58.   tar zxvf bcm2835-1.xx.tar.gz
  59.   cd bcm2835-1.xx
  60.   ./configure
  61.   make
  62.   sudo make check
  63.   sudo make install
  64.   \endcode
  65.  
  66.   \par Physical Addresses
  67.  
  68.   The functions bcm2835_peri_read(), bcm2835_peri_write() and bcm2835_peri_set_bits()
  69.   are low level peripheral register access functions. They are designed to use
  70.   physical addresses as described in section 1.2.3 ARM physical addresses
  71.   of the BCM2835 ARM Peripherals manual.
  72.   Physical addresses range from 0x20000000 to 0x20FFFFFF for peripherals. The bus
  73.   addresses for peripherals are set up to map onto the peripheral bus address range starting at
  74.   0x7E000000. Thus a peripheral advertised in the manual at bus address 0x7Ennnnnn is available at
  75.   physical address 0x20nnnnnn.
  76.  
  77.   On RPI 2, the peripheral addresses are different and the bcm2835 library gets them
  78.   from reading /proc/device-tree/soc/ranges. This is only availble with recent versions of the kernel on RPI 2.
  79.  
  80.   After initialisation, the base address of the various peripheral
  81.   registers are available with the following
  82.   externals:
  83.   bcm2835_gpio
  84.   bcm2835_pwm
  85.   bcm2835_clk
  86.   bcm2835_pads
  87.   bcm2835_spio0
  88.   bcm2835_st
  89.   bcm2835_bsc0
  90.   bcm2835_bsc1
  91.  
  92.   \par Pin Numbering
  93.  
  94.   The GPIO pin numbering as used by RPi is different to and inconsistent with the underlying
  95.   BCM 2835 chip pin numbering. http://e...content-available-to-author-only...x.org/RPi_BCM2835_GPIOs
  96.  
  97.   RPi has a 26 pin IDE header that provides access to some of the GPIO pins on the BCM 2835,
  98.   as well as power and ground pins. Not all GPIO pins on the BCM 2835 are available on the
  99.   IDE header.
  100.  
  101.   RPi Version 2 also has a P5 connector with 4 GPIO pins, 5V, 3.3V and Gnd.
  102.  
  103.   The functions in this library are designed to be passed the BCM 2835 GPIO pin number and _not_
  104.   the RPi pin number. There are symbolic definitions for each of the available pins
  105.   that you should use for convenience. See \ref RPiGPIOPin.
  106.  
  107.   \par SPI Pins
  108.  
  109.   The bcm2835_spi_* functions allow you to control the BCM 2835 SPI0 interface,
  110.   allowing you to send and received data by SPI (Serial Peripheral Interface).
  111.   For more information about SPI, see http://e...content-available-to-author-only...a.org/wiki/Serial_Peripheral_Interface_Bus
  112.  
  113.   When bcm2835_spi_begin() is called it changes the bahaviour of the SPI interface pins from their
  114.   default GPIO behaviour in order to support SPI. While SPI is in use, you will not be able
  115.   to control the state of the SPI pins through the usual bcm2835_spi_gpio_write().
  116.   When bcm2835_spi_end() is called, the SPI pins will all revert to inputs, and can then be
  117.   configured and controled with the usual bcm2835_gpio_* calls.
  118.  
  119.   The Raspberry Pi GPIO pins used for SPI are:
  120.  
  121.   - P1-19 (MOSI)
  122.   - P1-21 (MISO)
  123.   - P1-23 (CLK)
  124.   - P1-24 (CE0)
  125.   - P1-26 (CE1)
  126.  
  127.   \par I2C Pins
  128.  
  129.   The bcm2835_i2c_* functions allow you to control the BCM 2835 BSC interface,
  130.   allowing you to send and received data by I2C ("eye-squared cee"; generically referred to as "two-wire interface") .
  131.   For more information about I?C, see http://e...content-available-to-author-only...a.org/wiki/I%C2%B2C
  132.  
  133.   The Raspberry Pi V2 GPIO pins used for I2C are:
  134.  
  135.   - P1-03 (SDA)
  136.   - P1-05 (SLC)
  137.  
  138.   \par PWM
  139.  
  140.   The BCM2835 supports hardware PWM on a limited subset of GPIO pins. This bcm2835 library provides
  141.   functions for configuring and controlling PWM output on these pins.
  142.  
  143.   The BCM2835 contains 2 independent PWM channels (0 and 1), each of which be connnected to a limited subset of
  144.   GPIO pins. The following GPIO pins may be connected to the following PWM channels (from section 9.5):
  145.   \code
  146.   GPIO PIN RPi pin PWM Channel ALT FUN
  147.   12 0 0
  148.   13 1 0
  149.   18 1-12 0 5
  150.   19 1 5
  151.   40 0 0
  152.   41 1 0
  153.   45 1 0
  154.   52 0 1
  155.   53 1 1
  156.   \endcode
  157.   In order for a GPIO pin to emit output from its PWM channel, it must be set to the Alt Function given above.
  158.   Note carefully that current versions of the Raspberry Pi only expose one of these pins (GPIO 18 = RPi Pin 1-12)
  159.   on the IO headers, and therefore this is the only IO pin on the RPi that can be used for PWM.
  160.   Further it must be set to ALT FUN 5 to get PWM output.
  161.  
  162.   Both PWM channels are driven by the same PWM clock, whose clock dvider can be varied using
  163.   bcm2835_pwm_set_clock(). Each channel can be separately enabled with bcm2835_pwm_set_mode().
  164.   The average output of the PWM channel is determined by the ratio of DATA/RANGE for that channel.
  165.   Use bcm2835_pwm_set_range() to set the range and bcm2835_pwm_set_data() to set the data in that ratio
  166.  
  167.   Each PWM channel can run in either Balanced or Mark-Space mode. In Balanced mode, the hardware
  168.   sends a combination of clock pulses that results in an overall DATA pulses per RANGE pulses.
  169.   In Mark-Space mode, the hardware sets the output HIGH for DATA clock pulses wide, followed by
  170.   LOW for RANGE-DATA clock pulses.
  171.  
  172.   The PWM clock can be set to control the PWM pulse widths. The PWM clock is derived from
  173.   a 19.2MHz clock. You can set any divider, but some common ones are provided by the BCM2835_PWM_CLOCK_DIVIDER_*
  174.   values of \ref bcm2835PWMClockDivider.
  175.  
  176.   For example, say you wanted to drive a DC motor with PWM at about 1kHz,
  177.   and control the speed in 1/1024 increments from
  178.   0/1024 (stopped) through to 1024/1024 (full on). In that case you might set the
  179.   clock divider to be 16, and the RANGE to 1024. The pulse repetition frequency will be
  180.   1.2MHz/1024 = 1171.875Hz.
  181.  
  182.   \par Real Time performance constraints
  183.  
  184.   The bcm2835 is a library for user programs (i.e. they run in 'userland').
  185.   Such programs are not part of the kernel and are usually
  186.   subject to paging and swapping by the kernel while it does other things besides running your program.
  187.   This means that you should not expect to get real-time performance or
  188.   real-time timing constraints from such programs. In particular, there is no guarantee that the
  189.   bcm2835_delay() and bcm2835_delayMicroseconds() will return after exactly the time requested.
  190.   In fact, depending on other activity on the host, IO etc, you might get significantly longer delay times
  191.   than the one you asked for. So please dont expect to get exactly the time delay you request.
  192.  
  193.   Arjan reports that you can prevent swapping on Linux with the following code fragment:
  194.  
  195.   \code
  196.   struct sched_param sp;
  197.   memset(&sp, 0, sizeof(sp));
  198.   sp.sched_priority = sched_get_priority_max(SCHED_FIFO);
  199.   sched_setscheduler(0, SCHED_FIFO, &sp);
  200.   mlockall(MCL_CURRENT | MCL_FUTURE);
  201.   \endcode
  202.  
  203.   \par Bindings to other languages
  204.  
  205.   mikem has made Perl bindings available at CPAN:
  206.   http://s...content-available-to-author-only...n.org/~mikem/Device-BCM2835-1.9/lib/Device/BCM2835.pm
  207.   Matthew Baker has kindly made Python bindings available at:
  208.   https: github.com/mubeta06/py-libbcm2835
  209.   Gary Marks has created a Serial Peripheral Interface (SPI) command-line utility
  210.   for Raspberry Pi, based on the bcm2835 library. The
  211.   utility, spincl, is licensed under Open Source GNU GPLv3 by iP Solutions (http://i...content-available-to-author-only...p.com), as a
  212.   free download with source included: http://i...content-available-to-author-only...p.com/raspberry-pi-spi-utility/
  213.  
  214.   \par Open Source Licensing GPL V2
  215.  
  216.   This is the appropriate option if you want to share the source code of your
  217.   application with everyone you distribute it to, and you also want to give them
  218.   the right to share who uses it. If you wish to use this software under Open
  219.   Source Licensing, you must contribute all your source code to the open source
  220.   community in accordance with the GPL Version 2 when your application is
  221.   distributed. See http://w...content-available-to-author-only...u.org/copyleft/gpl.html and COPYING
  222.  
  223.   \par Acknowledgements
  224.  
  225.   Some of this code has been inspired by Dom and Gert.
  226.   The I2C code has been inspired by Alan Barr.
  227.  
  228.   \par Revision History
  229.  
  230.   \version 1.0 Initial release
  231.  
  232.   \version 1.1 Minor bug fixes
  233.  
  234.   \version 1.2 Added support for SPI
  235.  
  236.   \version 1.3 Added bcm2835_spi_transfern()
  237.  
  238.   \version 1.4 Fixed a problem that prevented SPI CE1 being used. Reported by David Robinson.
  239.  
  240.   \version 1.5 Added bcm2835_close() to deinit the library. Suggested by C?sar Ortiz
  241.  
  242.   \version 1.6 Document testing on 2012-07-15-wheezy-raspbian and Occidentalisv01
  243.   Functions bcm2835_gpio_ren(), bcm2835_gpio_fen(), bcm2835_gpio_hen()
  244.   bcm2835_gpio_len(), bcm2835_gpio_aren() and bcm2835_gpio_afen() now
  245.   changes only the pin specified. Other pins that were already previously
  246.   enabled stay enabled.
  247.   Added bcm2835_gpio_clr_ren(), bcm2835_gpio_clr_fen(), bcm2835_gpio_clr_hen()
  248.   bcm2835_gpio_clr_len(), bcm2835_gpio_clr_aren(), bcm2835_gpio_clr_afen()
  249.   to clear the enable for individual pins, suggested by Andreas Sundstrom.
  250.  
  251.   \version 1.7 Added bcm2835_spi_transfernb to support different buffers for read and write.
  252.  
  253.   \version 1.8 Improvements to read barrier, as suggested by maddin.
  254.  
  255.   \version 1.9 Improvements contributed by mikew:
  256.   I noticed that it was mallocing memory for the mmaps on /dev/mem.
  257.   It's not necessary to do that, you can just mmap the file directly,
  258.   so I've removed the mallocs (and frees).
  259.   I've also modified delayMicroseconds() to use nanosleep() for long waits,
  260.   and a busy wait on a high resolution timer for the rest. This is because
  261.   I've found that calling nanosleep() takes at least 100-200 us.
  262.   You need to link using '-lrt' using this version.
  263.   I've added some unsigned casts to the debug prints to silence compiler
  264.   warnings I was getting, fixed some typos, and changed the value of
  265.   BCM2835_PAD_HYSTERESIS_ENABLED to 0x08 as per Gert van Loo's doc at
  266.   http://w...content-available-to-author-only...d.com/doc/101830961/GPIO-Pads-Control2
  267.   Also added a define for the passwrd value that Gert says is needed to
  268.   change pad control settings.
  269.  
  270.   \version 1.10 Changed the names of the delay functions to bcm2835_delay()
  271.   and bcm2835_delayMicroseconds() to prevent collisions with wiringPi.
  272.   Macros to map delay()-> bcm2835_delay() and
  273.   Macros to map delayMicroseconds()-> bcm2835_delayMicroseconds(), which
  274.   can be disabled by defining BCM2835_NO_DELAY_COMPATIBILITY
  275.  
  276.   \version 1.11 Fixed incorrect link to download file
  277.  
  278.   \version 1.12 New GPIO pin definitions for RPi version 2 (which has a different GPIO mapping)
  279.  
  280.   \version 1.13 New GPIO pin definitions for RPi version 2 plug P5
  281.   Hardware base pointers are now available (after initialisation) externally as bcm2835_gpio
  282.   bcm2835_pwm bcm2835_clk bcm2835_pads bcm2835_spi0.
  283.  
  284.   \version 1.14 Now compiles even if CLOCK_MONOTONIC_RAW is not available, uses CLOCK_MONOTONIC instead.
  285.   Fixed errors in documentation of SPI divider frequencies based on 250MHz clock.
  286.   Reported by Ben Simpson.
  287.  
  288.   \version 1.15 Added bcm2835_close() to end of examples as suggested by Mark Wolfe.
  289.  
  290.   \version 1.16 Added bcm2835_gpio_set_multi, bcm2835_gpio_clr_multi and bcm2835_gpio_write_multi
  291.   to allow a mask of pins to be set all at once. Requested by Sebastian Loncar.
  292.  
  293.   \version 1.17 Added bcm2835_gpio_write_mask. Requested by Sebastian Loncar.
  294.  
  295.   \version 1.18 Added bcm2835_i2c_* functions. Changes to bcm2835_delayMicroseconds:
  296.   now uses the RPi system timer counter, instead of clock_gettime, for improved accuracy.
  297.   No need to link with -lrt now. Contributed by Arjan van Vught.
  298.   \version 1.19 Removed inlines added by previous patch since they don't seem to work everywhere.
  299.   Reported by olly.
  300.  
  301.   \version 1.20 Patch from Mark Dootson to close /dev/mem after access to the peripherals has been granted.
  302.  
  303.   \version 1.21 delayMicroseconds is now not susceptible to 32 bit timer overruns.
  304.   Patch courtesy Jeremy Mortis.
  305.  
  306.   \version 1.22 Fixed incorrect definition of BCM2835_GPFEN0 which broke the ability to set
  307.   falling edge events. Reported by Mark Dootson.
  308.  
  309.   \version 1.23 Added bcm2835_i2c_set_baudrate and bcm2835_i2c_read_register_rs.
  310.   Improvements to bcm2835_i2c_read and bcm2835_i2c_write functions
  311.   to fix ocasional reads not completing. Patched by Mark Dootson.
  312.  
  313.   \version 1.24 Mark Dootson p[atched a problem with his previously submitted code
  314.   under high load from other processes.
  315.  
  316.   \version 1.25 Updated author and distribution location details to airspayce.com
  317.  
  318.   \version 1.26 Added missing unmapmem for pads in bcm2835_close to prevent a memory leak.
  319.   Reported by Hartmut Henkel.
  320.  
  321.   \version 1.27 bcm2835_gpio_set_pad() no longer needs BCM2835_PAD_PASSWRD: it is
  322.   now automatically included.
  323.   Added suport for PWM mode with bcm2835_pwm_* functions.
  324.  
  325.   \version 1.28 Fixed a problem where bcm2835_spi_writenb() would have problems with transfers of more than
  326.   64 bytes dues to read buffer filling. Patched by Peter Würtz.
  327.  
  328.   \version 1.29 Further fix to SPI from Peter Würtz.
  329.  
  330.   \version 1.30 10 microsecond delays from bcm2835_spi_transfer and bcm2835_spi_transfern for
  331.   significant performance improvements, Patch by Alan Watson.
  332.  
  333.   \version 1.31 Fix a GCC warning about dummy variable, patched by Alan Watson. Thanks.
  334.  
  335.   \version 1.32 Added option I2C_V1 definition to compile for version 1 RPi.
  336.   By default I2C code is generated for the V2 RPi which has SDA1 and SCL1 connected.
  337.   Contributed by Malcolm Wiles based on work by Arvi Govindaraj.
  338.  
  339.   \version 1.33 Added command line utilities i2c and gpio to examples. Contributed by Shahrooz Shahparnia.
  340.  
  341.   \version 1.34 Added bcm2835_i2c_write_read_rs() which writes an arbitrary number of bytes,
  342.   sends a repeat start, and reads from the device. Contributed by Eduardo Steinhorst.
  343.  
  344.   \version 1.35 Fix build errors when compiled under Qt. Also performance improvements with SPI transfers. Contributed b Udo Klaas.
  345.  
  346.   \version 1.36 Make automake's test runner detect that we're skipping tests when not root, the second
  347.   one makes us skip the test when using fakeroot (as used when building
  348.   Debian packages). Contributed by Guido Günther.
  349.  
  350.   \version 1.37 Moved confiure.in to configure.ac as receommnded by autoreconf.<br>
  351.   Improvements to bcm2835_st_read to account for possible timer overflow, contributed by 'Ed'.<br>
  352.   Added definitions for Raspberry Pi B+ J8 header GPIO pins.<br>
  353.  
  354.   \version 1.38 Added bcm2835_regbase for the benefit of C# wrappers, patch by Frank Hommers <br>
  355.  
  356.   \version 1.39 Beta version of RPi2 compatibility. Not tested here on RPi2 hardware.
  357.   Testers please confirm correct operation on RPi2.<br>
  358.   Unneccessary 'volatile' qualifiers removed from all variables and signatures.<br>
  359.   Removed unsupportable PWM dividers, based on a report from Christophe Cecillon.<br>
  360.   Minor improvements to spi.c example.<br>
  361.  
  362.   \version 1.40 Correct operation on RPi2 has been confirmed.<br>
  363.   Fixed a number of compiler errors and warnings that occur when bcm2835.h is included
  364.   in code compiled with -Wall -Woverflow -Wstrict-overflow -Wshadow -Wextra -pedantic.
  365.   Reported by tlhackque.<br>
  366.   Fixed a problem where calling bcm2835_delayMicroseconds loops forever when debug is set. Reported by tlhackque.<br>
  367.   Reinstated use of volatile in 2 functions where there was a danger of lost reads or writes. Reported by tlhackque.<br>
  368.  
  369.   \version 1.41 Added BCM2835_VERSION macro and new function bcm2835_version(); Requested by tlhackque.<br>
  370.   Improvements to peripheral memory barriers as suggested by tlhackque.<br>
  371.   Reinstated some necessary volatile declarations as requested by tlhackque.<br>
  372.  
  373.   \version 1.42 Further improvements to memory barriers with the patient assistance and patches of tlhackque.<br>
  374.  
  375.   \author Mike McCauley (mikem@airspayce.com) DO NOT CONTACT THE AUTHOR DIRECTLY: USE THE LISTS
  376. */
  377.  
  378.  
  379. /* Defines for BCM2835 */
  380. #ifndef BCM2835_H
  381. #define BCM2835_H
  382.  
  383. #include <stdint.h>
  384.  
  385. #define BCM2835_VERSION 10042 /* Version 1.42 */
  386.  
  387. /* RPi 2 is ARM v7, and has DMB instruction.
  388.   Older RPis are ARM v6 and don't, so a coprocessor instruction must be used.
  389.   The odd test is so any newer processors will use DMB. I'm not sure, but assumed
  390.   that __ARM_ARCH_7_ implies __ARM_ARCH_6__. So the test is:
  391.   if not a V6 machine (all RPis before RPi 2), use DMB.
  392. */
  393. #if !( defined(__ARM_ARCH_6__) && !defined( __ARM_ARCH_7__ ) )
  394. #define BCM2835_HAVE_DMB
  395. #endif
  396.  
  397. /*! \defgroup constants Constants for passing to and from library functions
  398.   The values here are designed to be passed to various functions in the bcm2835 library.
  399.   @{
  400. */
  401.  
  402. /*! This means pin HIGH, true, 3.3volts on a pin. */
  403. #define HIGH 0x1
  404. /*! This means pin LOW, false, 0volts on a pin. */
  405. #define LOW 0x0
  406.  
  407. /*! Speed of the core clock core_clk */
  408. #define BCM2835_CORE_CLK_HZ 250000000 /*!< 250 MHz */
  409.  
  410. /*! On RPi2 with BCM2836, the base of the peripherals is read from a /proc file */
  411. #define BMC2835_RPI2_DT_FILENAME "/proc/device-tree/soc/ranges"
  412. /*! On RPi2, offset into BMC2835_RPI2_DT_FILENAME for the peripherals base address */
  413. #define BMC2835_RPI2_DT_PERI_BASE_ADDRESS_OFFSET 4
  414. /*! On RPi2, offset into BMC2835_RPI2_DT_FILENAME for the peripherals size address */
  415. #define BMC2835_RPI2_DT_PERI_SIZE_OFFSET 8
  416.  
  417. /*! Physical addresses for various peripheral register sets
  418.   Base Physical Address of the BCM 2835 peripheral registers
  419.   Note this is different for the RPi2 BCM2836, where this isderived from /proc/device-tree/soc/ranges
  420. */
  421. #define BCM2835_PERI_BASE 0x20000000
  422. /*! Size of the peripherals block on RPi 1 */
  423. #define BCM2835_PERI_SIZE 0x01000000
  424.  
  425. /*! Offsets for the bases of various peripherals within the peripherals block
  426.   / Base Address of the System Timer registers
  427. */
  428. #define BCM2835_ST_BASE 0x3000
  429. /*! Base Address of the Pads registers */
  430. #define BCM2835_GPIO_PADS 0x100000
  431. /*! Base Address of the Clock/timer registers */
  432. #define BCM2835_CLOCK_BASE 0x101000
  433. /*! Base Address of the GPIO registers */
  434. #define BCM2835_GPIO_BASE 0x200000
  435. /*! Base Address of the SPI0 registers */
  436. #define BCM2835_SPI0_BASE 0x204000
  437. /*! Base Address of the BSC0 registers */
  438. #define BCM2835_BSC0_BASE 0x205000
  439. /*! Base Address of the PWM registers */
  440. #define BCM2835_GPIO_PWM 0x20C000
  441. /*! Base Address of the BSC1 registers */
  442. #define BCM2835_BSC1_BASE 0x804000
  443.  
  444. /*! Physical address and size of the peripherals block
  445.   May be overridden on RPi2
  446. */
  447. extern uint32_t *bcm2835_peripherals_base;
  448. /*! Size of the peripherals block to be mapped */
  449. extern uint32_t bcm2835_peripherals_size;
  450.  
  451. /*! Virtual memory address of the mapped peripherals block */
  452. extern uint32_t *bcm2835_peripherals;
  453.  
  454. /*! Base of the ST (System Timer) registers.
  455.   Available after bcm2835_init has been called
  456. */
  457. extern volatile uint32_t *bcm2835_st;
  458.  
  459. /*! Base of the GPIO registers.
  460.   Available after bcm2835_init has been called
  461. */
  462. extern volatile uint32_t *bcm2835_gpio;
  463.  
  464. /*! Base of the PWM registers.
  465.   Available after bcm2835_init has been called
  466. */
  467. extern volatile uint32_t *bcm2835_pwm;
  468.  
  469. /*! Base of the CLK registers.
  470.   Available after bcm2835_init has been called
  471. */
  472. extern volatile uint32_t *bcm2835_clk;
  473.  
  474. /*! Base of the PADS registers.
  475.   Available after bcm2835_init has been called
  476. */
  477. extern volatile uint32_t *bcm2835_pads;
  478.  
  479. /*! Base of the SPI0 registers.
  480.   Available after bcm2835_init has been called
  481. */
  482. extern volatile uint32_t *bcm2835_spi0;
  483.  
  484. /*! Base of the BSC0 registers.
  485.   Available after bcm2835_init has been called
  486. */
  487. extern volatile uint32_t *bcm2835_bsc0;
  488.  
  489. /*! Base of the BSC1 registers.
  490.   Available after bcm2835_init has been called
  491. */
  492. extern volatile uint32_t *bcm2835_bsc1;
  493.  
  494. /*! \brief bcm2835RegisterBase
  495.   Register bases for bcm2835_regbase()
  496. */
  497. typedef enum
  498. {
  499. BCM2835_REGBASE_ST = 1, /*!< Base of the ST (System Timer) registers. */
  500. BCM2835_REGBASE_GPIO = 2, /*!< Base of the GPIO registers. */
  501. BCM2835_REGBASE_PWM = 3, /*!< Base of the PWM registers. */
  502. BCM2835_REGBASE_CLK = 4, /*!< Base of the CLK registers. */
  503. BCM2835_REGBASE_PADS = 5, /*!< Base of the PADS registers. */
  504. BCM2835_REGBASE_SPI0 = 6, /*! Base of the SPI0 registers. */
  505. BCM2835_REGBASE_BSC0 = 7, /*!< Base of the BSC0 registers. */
  506. BCM2835_REGBASE_BSC1 = 8 /*!< Base of the BSC1 registers. */
  507. } bcm2835RegisterBase;
  508.  
  509. /*! Size of memory page on RPi */
  510. #define BCM2835_PAGE_SIZE (4*1024)
  511. /*! Size of memory block on RPi */
  512. #define BCM2835_BLOCK_SIZE (4*1024)
  513.  
  514.  
  515. /* Defines for GPIO
  516.   The BCM2835 has 54 GPIO pins.
  517.   BCM2835 data sheet, Page 90 onwards.
  518. */
  519. /*! GPIO register offsets from BCM2835_GPIO_BASE.
  520.   Offsets into the GPIO Peripheral block in bytes per 6.1 Register View
  521. */
  522. #define BCM2835_GPFSEL0 0x0000 /*!< GPIO Function Select 0 */
  523. #define BCM2835_GPFSEL1 0x0004 /*!< GPIO Function Select 1 */
  524. #define BCM2835_GPFSEL2 0x0008 /*!< GPIO Function Select 2 */
  525. #define BCM2835_GPFSEL3 0x000c /*!< GPIO Function Select 3 */
  526. #define BCM2835_GPFSEL4 0x0010 /*!< GPIO Function Select 4 */
  527. #define BCM2835_GPFSEL5 0x0014 /*!< GPIO Function Select 5 */
  528. #define BCM2835_GPSET0 0x001c /*!< GPIO Pin Output Set 0 */
  529. #define BCM2835_GPSET1 0x0020 /*!< GPIO Pin Output Set 1 */
  530. #define BCM2835_GPCLR0 0x0028 /*!< GPIO Pin Output Clear 0 */
  531. #define BCM2835_GPCLR1 0x002c /*!< GPIO Pin Output Clear 1 */
  532. #define BCM2835_GPLEV0 0x0034 /*!< GPIO Pin Level 0 */
  533. #define BCM2835_GPLEV1 0x0038 /*!< GPIO Pin Level 1 */
  534. #define BCM2835_GPEDS0 0x0040 /*!< GPIO Pin Event Detect Status 0 */
  535. #define BCM2835_GPEDS1 0x0044 /*!< GPIO Pin Event Detect Status 1 */
  536. #define BCM2835_GPREN0 0x004c /*!< GPIO Pin Rising Edge Detect Enable 0 */
  537. #define BCM2835_GPREN1 0x0050 /*!< GPIO Pin Rising Edge Detect Enable 1 */
  538. #define BCM2835_GPFEN0 0x0058 /*!< GPIO Pin Falling Edge Detect Enable 0 */
  539. #define BCM2835_GPFEN1 0x005c /*!< GPIO Pin Falling Edge Detect Enable 1 */
  540. #define BCM2835_GPHEN0 0x0064 /*!< GPIO Pin High Detect Enable 0 */
  541. #define BCM2835_GPHEN1 0x0068 /*!< GPIO Pin High Detect Enable 1 */
  542. #define BCM2835_GPLEN0 0x0070 /*!< GPIO Pin Low Detect Enable 0 */
  543. #define BCM2835_GPLEN1 0x0074 /*!< GPIO Pin Low Detect Enable 1 */
  544. #define BCM2835_GPAREN0 0x007c /*!< GPIO Pin Async. Rising Edge Detect 0 */
  545. #define BCM2835_GPAREN1 0x0080 /*!< GPIO Pin Async. Rising Edge Detect 1 */
  546. #define BCM2835_GPAFEN0 0x0088 /*!< GPIO Pin Async. Falling Edge Detect 0 */
  547. #define BCM2835_GPAFEN1 0x008c /*!< GPIO Pin Async. Falling Edge Detect 1 */
  548. #define BCM2835_GPPUD 0x0094 /*!< GPIO Pin Pull-up/down Enable */
  549. #define BCM2835_GPPUDCLK0 0x0098 /*!< GPIO Pin Pull-up/down Enable Clock 0 */
  550. #define BCM2835_GPPUDCLK1 0x009c /*!< GPIO Pin Pull-up/down Enable Clock 1 */
  551.  
  552. /*! \brief bcm2835PortFunction
  553.   Port function select modes for bcm2835_gpio_fsel()
  554. */
  555. typedef enum
  556. {
  557. BCM2835_GPIO_FSEL_INPT = 0x00, /*!< Input 0b000 */
  558. BCM2835_GPIO_FSEL_OUTP = 0x01, /*!< Output 0b001 */
  559. BCM2835_GPIO_FSEL_ALT0 = 0x04, /*!< Alternate function 0 0b100 */
  560. BCM2835_GPIO_FSEL_ALT1 = 0x05, /*!< Alternate function 1 0b101 */
  561. BCM2835_GPIO_FSEL_ALT2 = 0x06, /*!< Alternate function 2 0b110, */
  562. BCM2835_GPIO_FSEL_ALT3 = 0x07, /*!< Alternate function 3 0b111 */
  563. BCM2835_GPIO_FSEL_ALT4 = 0x03, /*!< Alternate function 4 0b011 */
  564. BCM2835_GPIO_FSEL_ALT5 = 0x02, /*!< Alternate function 5 0b010 */
  565. BCM2835_GPIO_FSEL_MASK = 0x07 /*!< Function select bits mask 0b111 */
  566. } bcm2835FunctionSelect;
  567.  
  568. /*! \brief bcm2835PUDControl
  569.   Pullup/Pulldown defines for bcm2835_gpio_pud()
  570. */
  571. typedef enum
  572. {
  573. BCM2835_GPIO_PUD_OFF = 0x00, /*!< Off ? disable pull-up/down 0b00 */
  574. BCM2835_GPIO_PUD_DOWN = 0x01, /*!< Enable Pull Down control 0b01 */
  575. BCM2835_GPIO_PUD_UP = 0x02 /*!< Enable Pull Up control 0b10 */
  576. } bcm2835PUDControl;
  577.  
  578. /*! Pad control register offsets from BCM2835_GPIO_PADS */
  579. #define BCM2835_PADS_GPIO_0_27 0x002c /*!< Pad control register for pads 0 to 27 */
  580. #define BCM2835_PADS_GPIO_28_45 0x0030 /*!< Pad control register for pads 28 to 45 */
  581. #define BCM2835_PADS_GPIO_46_53 0x0034 /*!< Pad control register for pads 46 to 53 */
  582.  
  583. /*! Pad Control masks */
  584. #define BCM2835_PAD_PASSWRD (0x5A << 24) /*!< Password to enable setting pad mask */
  585. #define BCM2835_PAD_SLEW_RATE_UNLIMITED 0x10 /*!< Slew rate unlimited */
  586. #define BCM2835_PAD_HYSTERESIS_ENABLED 0x08 /*!< Hysteresis enabled */
  587. #define BCM2835_PAD_DRIVE_2mA 0x00 /*!< 2mA drive current */
  588. #define BCM2835_PAD_DRIVE_4mA 0x01 /*!< 4mA drive current */
  589. #define BCM2835_PAD_DRIVE_6mA 0x02 /*!< 6mA drive current */
  590. #define BCM2835_PAD_DRIVE_8mA 0x03 /*!< 8mA drive current */
  591. #define BCM2835_PAD_DRIVE_10mA 0x04 /*!< 10mA drive current */
  592. #define BCM2835_PAD_DRIVE_12mA 0x05 /*!< 12mA drive current */
  593. #define BCM2835_PAD_DRIVE_14mA 0x06 /*!< 14mA drive current */
  594. #define BCM2835_PAD_DRIVE_16mA 0x07 /*!< 16mA drive current */
  595.  
  596. /*! \brief bcm2835PadGroup
  597.   Pad group specification for bcm2835_gpio_pad()
  598. */
  599. typedef enum
  600. {
  601. BCM2835_PAD_GROUP_GPIO_0_27 = 0, /*!< Pad group for GPIO pads 0 to 27 */
  602. BCM2835_PAD_GROUP_GPIO_28_45 = 1, /*!< Pad group for GPIO pads 28 to 45 */
  603. BCM2835_PAD_GROUP_GPIO_46_53 = 2 /*!< Pad group for GPIO pads 46 to 53 */
  604. } bcm2835PadGroup;
  605.  
  606. /*! \brief GPIO Pin Numbers
  607.  
  608.   Here we define Raspberry Pin GPIO pins on P1 in terms of the underlying BCM GPIO pin numbers.
  609.   These can be passed as a pin number to any function requiring a pin.
  610.   Not all pins on the RPi 26 bin IDE plug are connected to GPIO pins
  611.   and some can adopt an alternate function.
  612.   RPi version 2 has some slightly different pinouts, and these are values RPI_V2_*.
  613.   RPi B+ has yet differnet pinouts and these are defined in RPI_BPLUS_*.
  614.   At bootup, pins 8 and 10 are set to UART0_TXD, UART0_RXD (ie the alt0 function) respectively
  615.   When SPI0 is in use (ie after bcm2835_spi_begin()), SPI0 pins are dedicated to SPI
  616.   and cant be controlled independently.
  617.   If you are using the RPi Compute Module, just use the GPIO number: there is no need to use one of these
  618.   symbolic names
  619. */
  620. typedef enum
  621. {
  622. RPI_GPIO_P1_03 = 0, /*!< Version 1, Pin P1-03 */
  623. RPI_GPIO_P1_05 = 1, /*!< Version 1, Pin P1-05 */
  624. RPI_GPIO_P1_07 = 4, /*!< Version 1, Pin P1-07 */
  625. RPI_GPIO_P1_08 = 14, /*!< Version 1, Pin P1-08, defaults to alt function 0 UART0_TXD */
  626. RPI_GPIO_P1_10 = 15, /*!< Version 1, Pin P1-10, defaults to alt function 0 UART0_RXD */
  627. RPI_GPIO_P1_11 = 17, /*!< Version 1, Pin P1-11 */
  628. RPI_GPIO_P1_12 = 18, /*!< Version 1, Pin P1-12, can be PWM channel 0 in ALT FUN 5 */
  629. RPI_GPIO_P1_13 = 21, /*!< Version 1, Pin P1-13 */
  630. RPI_GPIO_P1_15 = 22, /*!< Version 1, Pin P1-15 */
  631. RPI_GPIO_P1_16 = 23, /*!< Version 1, Pin P1-16 */
  632. RPI_GPIO_P1_18 = 24, /*!< Version 1, Pin P1-18 */
  633. RPI_GPIO_P1_19 = 10, /*!< Version 1, Pin P1-19, MOSI when SPI0 in use */
  634. RPI_GPIO_P1_21 = 9, /*!< Version 1, Pin P1-21, MISO when SPI0 in use */
  635. RPI_GPIO_P1_22 = 25, /*!< Version 1, Pin P1-22 */
  636. RPI_GPIO_P1_23 = 11, /*!< Version 1, Pin P1-23, CLK when SPI0 in use */
  637. RPI_GPIO_P1_24 = 8, /*!< Version 1, Pin P1-24, CE0 when SPI0 in use */
  638. RPI_GPIO_P1_26 = 7, /*!< Version 1, Pin P1-26, CE1 when SPI0 in use */
  639.  
  640. /* RPi Version 2 */
  641. RPI_V2_GPIO_P1_03 = 2, /*!< Version 2, Pin P1-03 */
  642. RPI_V2_GPIO_P1_05 = 3, /*!< Version 2, Pin P1-05 */
  643. RPI_V2_GPIO_P1_07 = 4, /*!< Version 2, Pin P1-07 */
  644. RPI_V2_GPIO_P1_08 = 14, /*!< Version 2, Pin P1-08, defaults to alt function 0 UART0_TXD */
  645. RPI_V2_GPIO_P1_10 = 15, /*!< Version 2, Pin P1-10, defaults to alt function 0 UART0_RXD */
  646. RPI_V2_GPIO_P1_11 = 17, /*!< Version 2, Pin P1-11 */
  647. RPI_V2_GPIO_P1_12 = 18, /*!< Version 2, Pin P1-12, can be PWM channel 0 in ALT FUN 5 */
  648. RPI_V2_GPIO_P1_13 = 27, /*!< Version 2, Pin P1-13 */
  649. RPI_V2_GPIO_P1_15 = 22, /*!< Version 2, Pin P1-15 */
  650. RPI_V2_GPIO_P1_16 = 23, /*!< Version 2, Pin P1-16 */
  651. RPI_V2_GPIO_P1_18 = 24, /*!< Version 2, Pin P1-18 */
  652. RPI_V2_GPIO_P1_19 = 10, /*!< Version 2, Pin P1-19, MOSI when SPI0 in use */
  653. RPI_V2_GPIO_P1_21 = 9, /*!< Version 2, Pin P1-21, MISO when SPI0 in use */
  654. RPI_V2_GPIO_P1_22 = 25, /*!< Version 2, Pin P1-22 */
  655. RPI_V2_GPIO_P1_23 = 11, /*!< Version 2, Pin P1-23, CLK when SPI0 in use */
  656. RPI_V2_GPIO_P1_24 = 8, /*!< Version 2, Pin P1-24, CE0 when SPI0 in use */
  657. RPI_V2_GPIO_P1_26 = 7, /*!< Version 2, Pin P1-26, CE1 when SPI0 in use */
  658.  
  659. /* RPi Version 2, new plug P5 */
  660. RPI_V2_GPIO_P5_03 = 28, /*!< Version 2, Pin P5-03 */
  661. RPI_V2_GPIO_P5_04 = 29, /*!< Version 2, Pin P5-04 */
  662. RPI_V2_GPIO_P5_05 = 30, /*!< Version 2, Pin P5-05 */
  663. RPI_V2_GPIO_P5_06 = 31, /*!< Version 2, Pin P5-06 */
  664.  
  665. /* RPi B+ J8 header */
  666. RPI_BPLUS_GPIO_J8_03 = 2, /*!< B+, Pin J8-03 */
  667. RPI_BPLUS_GPIO_J8_05 = 3, /*!< B+, Pin J8-05 */
  668. RPI_BPLUS_GPIO_J8_07 = 4, /*!< B+, Pin J8-07 */
  669. RPI_BPLUS_GPIO_J8_08 = 14, /*!< B+, Pin J8-08, defaults to alt function 0 UART0_TXD */
  670. RPI_BPLUS_GPIO_J8_10 = 15, /*!< B+, Pin J8-10, defaults to alt function 0 UART0_RXD */
  671. RPI_BPLUS_GPIO_J8_11 = 17, /*!< B+, Pin J8-11 */
  672. RPI_BPLUS_GPIO_J8_12 = 18, /*!< B+, Pin J8-12, can be PWM channel 0 in ALT FUN 5 */
  673. RPI_BPLUS_GPIO_J8_13 = 27, /*!< B+, Pin J8-13 */
  674. RPI_BPLUS_GPIO_J8_15 = 22, /*!< B+, Pin J8-15 */
  675. RPI_BPLUS_GPIO_J8_16 = 23, /*!< B+, Pin J8-16 */
  676. RPI_BPLUS_GPIO_J8_18 = 24, /*!< B+, Pin J8-18 */
  677. RPI_BPLUS_GPIO_J8_19 = 10, /*!< B+, Pin J8-19, MOSI when SPI0 in use */
  678. RPI_BPLUS_GPIO_J8_21 = 9, /*!< B+, Pin J8-21, MISO when SPI0 in use */
  679. RPI_BPLUS_GPIO_J8_22 = 25, /*!< B+, Pin J8-22 */
  680. RPI_BPLUS_GPIO_J8_23 = 11, /*!< B+, Pin J8-23, CLK when SPI0 in use */
  681. RPI_BPLUS_GPIO_J8_24 = 8, /*!< B+, Pin J8-24, CE0 when SPI0 in use */
  682. RPI_BPLUS_GPIO_J8_26 = 7, /*!< B+, Pin J8-26, CE1 when SPI0 in use */
  683. RPI_BPLUS_GPIO_J8_29 = 5, /*!< B+, Pin J8-29, */
  684. RPI_BPLUS_GPIO_J8_31 = 6, /*!< B+, Pin J8-31, */
  685. RPI_BPLUS_GPIO_J8_32 = 12, /*!< B+, Pin J8-32, */
  686. RPI_BPLUS_GPIO_J8_33 = 13, /*!< B+, Pin J8-33, */
  687. RPI_BPLUS_GPIO_J8_35 = 19, /*!< B+, Pin J8-35, */
  688. RPI_BPLUS_GPIO_J8_36 = 16, /*!< B+, Pin J8-36, */
  689. RPI_BPLUS_GPIO_J8_37 = 26, /*!< B+, Pin J8-37, */
  690. RPI_BPLUS_GPIO_J8_38 = 20, /*!< B+, Pin J8-38, */
  691. RPI_BPLUS_GPIO_J8_40 = 21 /*!< B+, Pin J8-40, */
  692. } RPiGPIOPin;
  693.  
  694. /* Defines for SPI
  695.   GPIO register offsets from BCM2835_SPI0_BASE.
  696.   Offsets into the SPI Peripheral block in bytes per 10.5 SPI Register Map
  697. */
  698. #define BCM2835_SPI0_CS 0x0000 /*!< SPI Master Control and Status */
  699. #define BCM2835_SPI0_FIFO 0x0004 /*!< SPI Master TX and RX FIFOs */
  700. #define BCM2835_SPI0_CLK 0x0008 /*!< SPI Master Clock Divider */
  701. #define BCM2835_SPI0_DLEN 0x000c /*!< SPI Master Data Length */
  702. #define BCM2835_SPI0_LTOH 0x0010 /*!< SPI LOSSI mode TOH */
  703. #define BCM2835_SPI0_DC 0x0014 /*!< SPI DMA DREQ Controls */
  704.  
  705. /* Register masks for SPI0_CS */
  706. #define BCM2835_SPI0_CS_LEN_LONG 0x02000000 /*!< Enable Long data word in Lossi mode if DMA_LEN is set */
  707. #define BCM2835_SPI0_CS_DMA_LEN 0x01000000 /*!< Enable DMA mode in Lossi mode */
  708. #define BCM2835_SPI0_CS_CSPOL2 0x00800000 /*!< Chip Select 2 Polarity */
  709. #define BCM2835_SPI0_CS_CSPOL1 0x00400000 /*!< Chip Select 1 Polarity */
  710. #define BCM2835_SPI0_CS_CSPOL0 0x00200000 /*!< Chip Select 0 Polarity */
  711. #define BCM2835_SPI0_CS_RXF 0x00100000 /*!< RXF - RX FIFO Full */
  712. #define BCM2835_SPI0_CS_RXR 0x00080000 /*!< RXR RX FIFO needs Reading (full) */
  713. #define BCM2835_SPI0_CS_TXD 0x00040000 /*!< TXD TX FIFO can accept Data */
  714. #define BCM2835_SPI0_CS_RXD 0x00020000 /*!< RXD RX FIFO contains Data */
  715. #define BCM2835_SPI0_CS_DONE 0x00010000 /*!< Done transfer Done */
  716. #define BCM2835_SPI0_CS_TE_EN 0x00008000 /*!< Unused */
  717. #define BCM2835_SPI0_CS_LMONO 0x00004000 /*!< Unused */
  718. #define BCM2835_SPI0_CS_LEN 0x00002000 /*!< LEN LoSSI enable */
  719. #define BCM2835_SPI0_CS_REN 0x00001000 /*!< REN Read Enable */
  720. #define BCM2835_SPI0_CS_ADCS 0x00000800 /*!< ADCS Automatically Deassert Chip Select */
  721. #define BCM2835_SPI0_CS_INTR 0x00000400 /*!< INTR Interrupt on RXR */
  722. #define BCM2835_SPI0_CS_INTD 0x00000200 /*!< INTD Interrupt on Done */
  723. #define BCM2835_SPI0_CS_DMAEN 0x00000100 /*!< DMAEN DMA Enable */
  724. #define BCM2835_SPI0_CS_TA 0x00000080 /*!< Transfer Active */
  725. #define BCM2835_SPI0_CS_CSPOL 0x00000040 /*!< Chip Select Polarity */
  726. #define BCM2835_SPI0_CS_CLEAR 0x00000030 /*!< Clear FIFO Clear RX and TX */
  727. #define BCM2835_SPI0_CS_CLEAR_RX 0x00000020 /*!< Clear FIFO Clear RX */
  728. #define BCM2835_SPI0_CS_CLEAR_TX 0x00000010 /*!< Clear FIFO Clear TX */
  729. #define BCM2835_SPI0_CS_CPOL 0x00000008 /*!< Clock Polarity */
  730. #define BCM2835_SPI0_CS_CPHA 0x00000004 /*!< Clock Phase */
  731. #define BCM2835_SPI0_CS_CS 0x00000003 /*!< Chip Select */
  732.  
  733. /*! \brief bcm2835SPIBitOrder SPI Bit order
  734.   Specifies the SPI data bit ordering for bcm2835_spi_setBitOrder()
  735. */
  736. typedef enum
  737. {
  738. BCM2835_SPI_BIT_ORDER_LSBFIRST = 0, /*!< LSB First */
  739. BCM2835_SPI_BIT_ORDER_MSBFIRST = 1 /*!< MSB First */
  740. }bcm2835SPIBitOrder;
  741.  
  742. /*! \brief SPI Data mode
  743.   Specify the SPI data mode to be passed to bcm2835_spi_setDataMode()
  744. */
  745. typedef enum
  746. {
  747. BCM2835_SPI_MODE0 = 0, /*!< CPOL = 0, CPHA = 0 */
  748. BCM2835_SPI_MODE1 = 1, /*!< CPOL = 0, CPHA = 1 */
  749. BCM2835_SPI_MODE2 = 2, /*!< CPOL = 1, CPHA = 0 */
  750. BCM2835_SPI_MODE3 = 3 /*!< CPOL = 1, CPHA = 1 */
  751. }bcm2835SPIMode;
  752.  
  753. /*! \brief bcm2835SPIChipSelect
  754.   Specify the SPI chip select pin(s)
  755. */
  756. typedef enum
  757. {
  758. BCM2835_SPI_CS0 = 0, /*!< Chip Select 0 */
  759. BCM2835_SPI_CS1 = 1, /*!< Chip Select 1 */
  760. BCM2835_SPI_CS2 = 2, /*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */
  761. BCM2835_SPI_CS_NONE = 3 /*!< No CS, control it yourself */
  762. } bcm2835SPIChipSelect;
  763.  
  764. /*! \brief bcm2835SPIClockDivider
  765.   Specifies the divider used to generate the SPI clock from the system clock.
  766.   Figures below give the divider, clock period and clock frequency.
  767.   Clock divided is based on nominal base clock rate of 250MHz
  768.   It is reported that (contrary to the documentation) any even divider may used.
  769.   The frequencies shown for each divider have been confirmed by measurement
  770. */
  771. typedef enum
  772. {
  773. BCM2835_SPI_CLOCK_DIVIDER_65536 = 0, /*!< 65536 = 262.144us = 3.814697260kHz */
  774. BCM2835_SPI_CLOCK_DIVIDER_32768 = 32768, /*!< 32768 = 131.072us = 7.629394531kHz */
  775. BCM2835_SPI_CLOCK_DIVIDER_16384 = 16384, /*!< 16384 = 65.536us = 15.25878906kHz */
  776. BCM2835_SPI_CLOCK_DIVIDER_8192 = 8192, /*!< 8192 = 32.768us = 30/51757813kHz */
  777. BCM2835_SPI_CLOCK_DIVIDER_4096 = 4096, /*!< 4096 = 16.384us = 61.03515625kHz */
  778. BCM2835_SPI_CLOCK_DIVIDER_2048 = 2048, /*!< 2048 = 8.192us = 122.0703125kHz */
  779. BCM2835_SPI_CLOCK_DIVIDER_1024 = 1024, /*!< 1024 = 4.096us = 244.140625kHz */
  780. BCM2835_SPI_CLOCK_DIVIDER_512 = 512, /*!< 512 = 2.048us = 488.28125kHz */
  781. BCM2835_SPI_CLOCK_DIVIDER_256 = 256, /*!< 256 = 1.024us = 976.5625MHz */
  782. BCM2835_SPI_CLOCK_DIVIDER_128 = 128, /*!< 128 = 512ns = = 1.953125MHz */
  783. BCM2835_SPI_CLOCK_DIVIDER_64 = 64, /*!< 64 = 256ns = 3.90625MHz */
  784. BCM2835_SPI_CLOCK_DIVIDER_32 = 32, /*!< 32 = 128ns = 7.8125MHz */
  785. BCM2835_SPI_CLOCK_DIVIDER_16 = 16, /*!< 16 = 64ns = 15.625MHz */
  786. BCM2835_SPI_CLOCK_DIVIDER_8 = 8, /*!< 8 = 32ns = 31.25MHz */
  787. BCM2835_SPI_CLOCK_DIVIDER_4 = 4, /*!< 4 = 16ns = 62.5MHz */
  788. BCM2835_SPI_CLOCK_DIVIDER_2 = 2, /*!< 2 = 8ns = 125MHz, fastest you can get */
  789. BCM2835_SPI_CLOCK_DIVIDER_1 = 1 /*!< 1 = 262.144us = 3.814697260kHz, same as 0/65536 */
  790. } bcm2835SPIClockDivider;
  791.  
  792. /* Defines for I2C
  793.   GPIO register offsets from BCM2835_BSC*_BASE.
  794.   Offsets into the BSC Peripheral block in bytes per 3.1 BSC Register Map
  795. */
  796. #define BCM2835_BSC_C 0x0000 /*!< BSC Master Control */
  797. #define BCM2835_BSC_S 0x0004 /*!< BSC Master Status */
  798. #define BCM2835_BSC_DLEN 0x0008 /*!< BSC Master Data Length */
  799. #define BCM2835_BSC_A 0x000c /*!< BSC Master Slave Address */
  800. #define BCM2835_BSC_FIFO 0x0010 /*!< BSC Master Data FIFO */
  801. #define BCM2835_BSC_DIV 0x0014 /*!< BSC Master Clock Divider */
  802. #define BCM2835_BSC_DEL 0x0018 /*!< BSC Master Data Delay */
  803. #define BCM2835_BSC_CLKT 0x001c /*!< BSC Master Clock Stretch Timeout */
  804.  
  805. /* Register masks for BSC_C */
  806. #define BCM2835_BSC_C_I2CEN 0x00008000 /*!< I2C Enable, 0 = disabled, 1 = enabled */
  807. #define BCM2835_BSC_C_INTR 0x00000400 /*!< Interrupt on RX */
  808. #define BCM2835_BSC_C_INTT 0x00000200 /*!< Interrupt on TX */
  809. #define BCM2835_BSC_C_INTD 0x00000100 /*!< Interrupt on DONE */
  810. #define BCM2835_BSC_C_ST 0x00000080 /*!< Start transfer, 1 = Start a new transfer */
  811. #define BCM2835_BSC_C_CLEAR_1 0x00000020 /*!< Clear FIFO Clear */
  812. #define BCM2835_BSC_C_CLEAR_2 0x00000010 /*!< Clear FIFO Clear */
  813. #define BCM2835_BSC_C_READ 0x00000001 /*!< Read transfer */
  814.  
  815. /* Register masks for BSC_S */
  816. #define BCM2835_BSC_S_CLKT 0x00000200 /*!< Clock stretch timeout */
  817. #define BCM2835_BSC_S_ERR 0x00000100 /*!< ACK error */
  818. #define BCM2835_BSC_S_RXF 0x00000080 /*!< RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
  819. #define BCM2835_BSC_S_TXE 0x00000040 /*!< TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
  820. #define BCM2835_BSC_S_RXD 0x00000020 /*!< RXD FIFO contains data */
  821. #define BCM2835_BSC_S_TXD 0x00000010 /*!< TXD FIFO can accept data */
  822. #define BCM2835_BSC_S_RXR 0x00000008 /*!< RXR FIFO needs reading (full) */
  823. #define BCM2835_BSC_S_TXW 0x00000004 /*!< TXW FIFO needs writing (full) */
  824. #define BCM2835_BSC_S_DONE 0x00000002 /*!< Transfer DONE */
  825. #define BCM2835_BSC_S_TA 0x00000001 /*!< Transfer Active */
  826.  
  827. #define BCM2835_BSC_FIFO_SIZE 16 /*!< BSC FIFO size */
  828.  
  829. /*! \brief bcm2835I2CClockDivider
  830.   Specifies the divider used to generate the I2C clock from the system clock.
  831.   Clock divided is based on nominal base clock rate of 250MHz
  832. */
  833. typedef enum
  834. {
  835. BCM2835_I2C_CLOCK_DIVIDER_2500 = 2500, /*!< 2500 = 10us = 100 kHz */
  836. BCM2835_I2C_CLOCK_DIVIDER_626 = 626, /*!< 622 = 2.504us = 399.3610 kHz */
  837. BCM2835_I2C_CLOCK_DIVIDER_150 = 150, /*!< 150 = 60ns = 1.666 MHz (default at reset) */
  838. BCM2835_I2C_CLOCK_DIVIDER_148 = 148 /*!< 148 = 59ns = 1.689 MHz */
  839. } bcm2835I2CClockDivider;
  840.  
  841. /*! \brief bcm2835I2CReasonCodes
  842.   Specifies the reason codes for the bcm2835_i2c_write and bcm2835_i2c_read functions.
  843. */
  844. typedef enum
  845. {
  846. BCM2835_I2C_REASON_OK = 0x00, /*!< Success */
  847. BCM2835_I2C_REASON_ERROR_NACK = 0x01, /*!< Received a NACK */
  848. BCM2835_I2C_REASON_ERROR_CLKT = 0x02, /*!< Received Clock Stretch Timeout */
  849. BCM2835_I2C_REASON_ERROR_DATA = 0x04 /*!< Not all data is sent / received */
  850. } bcm2835I2CReasonCodes;
  851.  
  852. /* Defines for ST
  853.   GPIO register offsets from BCM2835_ST_BASE.
  854.   Offsets into the ST Peripheral block in bytes per 12.1 System Timer Registers
  855.   The System Timer peripheral provides four 32-bit timer channels and a single 64-bit free running counter.
  856.   BCM2835_ST_CLO is the System Timer Counter Lower bits register.
  857.   The system timer free-running counter lower register is a read-only register that returns the current value
  858.   of the lower 32-bits of the free running counter.
  859.   BCM2835_ST_CHI is the System Timer Counter Upper bits register.
  860.   The system timer free-running counter upper register is a read-only register that returns the current value
  861.   of the upper 32-bits of the free running counter.
  862. */
  863. #define BCM2835_ST_CS 0x0000 /*!< System Timer Control/Status */
  864. #define BCM2835_ST_CLO 0x0004 /*!< System Timer Counter Lower 32 bits */
  865. #define BCM2835_ST_CHI 0x0008 /*!< System Timer Counter Upper 32 bits */
  866.  
  867. /*! @} */
  868.  
  869.  
  870. /* Defines for PWM, word offsets (ie 4 byte multiples) */
  871. #define BCM2835_PWM_CONTROL 0
  872. #define BCM2835_PWM_STATUS 1
  873. #define BCM2835_PWM_DMAC 2
  874. #define BCM2835_PWM0_RANGE 4
  875. #define BCM2835_PWM0_DATA 5
  876. #define BCM2835_PWM_FIF1 6
  877. #define BCM2835_PWM1_RANGE 8
  878. #define BCM2835_PWM1_DATA 9
  879.  
  880. /* Defines for PWM Clock, word offsets (ie 4 byte multiples) */
  881. #define BCM2835_PWMCLK_CNTL 40
  882. #define BCM2835_PWMCLK_DIV 41
  883. #define BCM2835_PWM_PASSWRD (0x5A << 24) /*!< Password to enable setting PWM clock */
  884.  
  885. #define BCM2835_PWM1_MS_MODE 0x8000 /*!< Run in Mark/Space mode */
  886. #define BCM2835_PWM1_USEFIFO 0x2000 /*!< Data from FIFO */
  887. #define BCM2835_PWM1_REVPOLAR 0x1000 /*!< Reverse polarity */
  888. #define BCM2835_PWM1_OFFSTATE 0x0800 /*!< Ouput Off state */
  889. #define BCM2835_PWM1_REPEATFF 0x0400 /*!< Repeat last value if FIFO empty */
  890. #define BCM2835_PWM1_SERIAL 0x0200 /*!< Run in serial mode */
  891. #define BCM2835_PWM1_ENABLE 0x0100 /*!< Channel Enable */
  892.  
  893. #define BCM2835_PWM0_MS_MODE 0x0080 /*!< Run in Mark/Space mode */
  894. #define BCM2835_PWM_CLEAR_FIFO 0x0040 /*!< Clear FIFO */
  895. #define BCM2835_PWM0_USEFIFO 0x0020 /*!< Data from FIFO */
  896. #define BCM2835_PWM0_REVPOLAR 0x0010 /*!< Reverse polarity */
  897. #define BCM2835_PWM0_OFFSTATE 0x0008 /*!< Ouput Off state */
  898. #define BCM2835_PWM0_REPEATFF 0x0004 /*!< Repeat last value if FIFO empty */
  899. #define BCM2835_PWM0_SERIAL 0x0002 /*!< Run in serial mode */
  900. #define BCM2835_PWM0_ENABLE 0x0001 /*!< Channel Enable */
  901.  
  902. /*! \brief bcm2835PWMClockDivider
  903.   Specifies the divider used to generate the PWM clock from the system clock.
  904.   Figures below give the divider, clock period and clock frequency.
  905.   Clock divided is based on nominal PWM base clock rate of 19.2MHz
  906.   The frequencies shown for each divider have been confirmed by measurement
  907. */
  908. typedef enum
  909. {
  910. BCM2835_PWM_CLOCK_DIVIDER_2048 = 2048, /*!< 2048 = 9.375kHz */
  911. BCM2835_PWM_CLOCK_DIVIDER_1024 = 1024, /*!< 1024 = 18.75kHz */
  912. BCM2835_PWM_CLOCK_DIVIDER_512 = 512, /*!< 512 = 37.5kHz */
  913. BCM2835_PWM_CLOCK_DIVIDER_256 = 256, /*!< 256 = 75kHz */
  914. BCM2835_PWM_CLOCK_DIVIDER_128 = 128, /*!< 128 = 150kHz */
  915. BCM2835_PWM_CLOCK_DIVIDER_64 = 64, /*!< 64 = 300kHz */
  916. BCM2835_PWM_CLOCK_DIVIDER_32 = 32, /*!< 32 = 600.0kHz */
  917. BCM2835_PWM_CLOCK_DIVIDER_16 = 16, /*!< 16 = 1.2MHz */
  918. BCM2835_PWM_CLOCK_DIVIDER_8 = 8, /*!< 8 = 2.4MHz */
  919. BCM2835_PWM_CLOCK_DIVIDER_4 = 4, /*!< 4 = 4.8MHz */
  920. BCM2835_PWM_CLOCK_DIVIDER_2 = 2, /*!< 2 = 9.6MHz, fastest you can get */
  921. BCM2835_PWM_CLOCK_DIVIDER_1 = 1 /*!< 1 = 4.6875kHz, same as divider 4096 */
  922. } bcm2835PWMClockDivider;
  923.  
  924. /* Historical name compatibility */
  925. #ifndef BCM2835_NO_DELAY_COMPATIBILITY
  926. #define delay(x) bcm2835_delay(x)
  927. #define delayMicroseconds(x) bcm2835_delayMicroseconds(x)
  928. #endif
  929.  
  930. #ifdef __cplusplus
  931. extern "C" {
  932. #endif
  933.  
  934. /*! \defgroup init Library initialisation and management
  935.   These functions allow you to intialise and control the bcm2835 library
  936.   @{
  937.   */
  938.  
  939. /*! Initialise the library by opening /dev/mem and getting pointers to the
  940.   internal memory for BCM 2835 device registers. You must call this (successfully)
  941.   before calling any other
  942.   functions in this library (except bcm2835_set_debug).
  943.   If bcm2835_init() fails by returning 0,
  944.   calling any other function may result in crashes or other failures.
  945.   Prints messages to stderr in case of errors.
  946.   \return 1 if successful else 0
  947.   */
  948. extern int bcm2835_init(void);
  949.  
  950. /*! Close the library, deallocating any allocated memory and closing /dev/mem
  951.   \return 1 if successful else 0
  952.   */
  953. extern int bcm2835_close(void);
  954.  
  955. /*! Sets the debug level of the library.
  956.   A value of 1 prevents mapping to /dev/mem, and makes the library print out
  957.   what it would do, rather than accessing the GPIO registers.
  958.   A value of 0, the default, causes normal operation.
  959.   Call this before calling bcm2835_init();
  960.   \param[in] debug The new debug level. 1 means debug
  961.   */
  962. extern void bcm2835_set_debug(uint8_t debug);
  963.  
  964. /*! Returns the version number of the library, same as BCM2835_VERSION
  965.   \return the current library version number
  966.   */
  967. extern unsigned int bcm2835_version(void);
  968.  
  969. /*! @} */
  970.  
  971. /*! \defgroup lowlevel Low level register access
  972.   These functions provide low level register access, and should not generally
  973.   need to be used
  974.  
  975.   @{
  976.   */
  977.  
  978. /*! Gets the base of a register
  979.   \param[in] regbase You can use one of the common values BCM2835_REGBASE_*
  980.   in \ref bcm2835RegisterBase
  981.   \return the register base
  982.   \sa Physical Addresses
  983.   */
  984. extern uint32_t* bcm2835_regbase(uint8_t regbase);
  985.  
  986. /*! Reads 32 bit value from a peripheral address WITH a memory barrier before and after each read.
  987.   This is safe, but slow. The MB before protects this read from any in-flight reads that didn't
  988.   use a MB. The MB after protects subsequent reads from another peripheral.
  989.  
  990.   \param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.
  991.   \return the value read from the 32 bit register
  992.   \sa Physical Addresses
  993.   */
  994. extern uint32_t bcm2835_peri_read(volatile uint32_t* paddr);
  995.  
  996. /*! Reads 32 bit value from a peripheral address WITHOUT the read barriers
  997.   You should only use this when:
  998.   o your code has previously called bcm2835_peri_read() for a register
  999.   within the same peripheral, and no read or write to another peripheral has occurred since.
  1000.   o your code has called bcm2835_memory_barrier() since the last access to ANOTHER peripheral.
  1001.  
  1002.   \param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.
  1003.   \return the value read from the 32 bit register
  1004.   \sa Physical Addresses
  1005.   */
  1006. extern uint32_t bcm2835_peri_read_nb(volatile uint32_t* paddr);
  1007.  
  1008.  
  1009. /*! Writes 32 bit value from a peripheral address WITH a memory barrier before and after each write
  1010.   This is safe, but slow. The MB before ensures that any in-flight write to another peripheral
  1011.   completes before this write is issued. The MB after ensures that subsequent reads and writes
  1012.   to another peripheral will see the effect of this write.
  1013.  
  1014.   This is a tricky optimization; if you aren't sure, use the barrier version.
  1015.  
  1016.   \param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.
  1017.   \param[in] value The 32 bit value to write
  1018.   \sa Physical Addresses
  1019.   */
  1020. extern void bcm2835_peri_write(volatile uint32_t* paddr, uint32_t value);
  1021.  
  1022. /*! Writes 32 bit value from a peripheral address without the write barrier
  1023.   You should only use this when:
  1024.   o your code has previously called bcm2835_peri_write() for a register
  1025.   within the same peripheral, and no other peripheral access has occurred since.
  1026.   o your code has called bcm2835_memory_barrier() since the last access to ANOTHER peripheral.
  1027.  
  1028.   This is a tricky optimization; if you aren't sure, use the barrier version.
  1029.  
  1030.   \param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.
  1031.   \param[in] value The 32 bit value to write
  1032.   \sa Physical Addresses
  1033.   */
  1034. extern void bcm2835_peri_write_nb(volatile uint32_t* paddr, uint32_t value);
  1035.  
  1036. /*! Alters a number of bits in a 32 peripheral regsiter.
  1037.   It reads the current valu and then alters the bits defines as 1 in mask,
  1038.   according to the bit value in value.
  1039.   All other bits that are 0 in the mask are unaffected.
  1040.   Use this to alter a subset of the bits in a register.
  1041.   Memory barriers are used. Note that this is not atomic; an interrupt
  1042.   routine can cause unexpected results.
  1043.   \param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.
  1044.   \param[in] value The 32 bit value to write, masked in by mask.
  1045.   \param[in] mask Bitmask that defines the bits that will be altered in the register.
  1046.   \sa Physical Addresses
  1047.   */
  1048. extern void bcm2835_peri_set_bits(volatile uint32_t* paddr, uint32_t value, uint32_t mask);
  1049. /*! @} end of lowlevel */
  1050.  
  1051. /*! \defgroup gpio GPIO register access
  1052.   These functions allow you to control the GPIO interface. You can set the
  1053.   function of each GPIO pin, read the input state and set the output state.
  1054.   @{
  1055.   */
  1056.  
  1057. /*! Sets the Function Select register for the given pin, which configures
  1058.   the pin as Input, Output or one of the 6 alternate functions.
  1059.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1060.   \param[in] mode Mode to set the pin to, one of BCM2835_GPIO_FSEL_* from \ref bcm2835FunctionSelect
  1061.   */
  1062. extern void bcm2835_gpio_fsel(uint8_t pin, uint8_t mode);
  1063.  
  1064. /*! Sets the specified pin output to
  1065.   HIGH.
  1066.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1067.   \sa bcm2835_gpio_write()
  1068.   */
  1069. extern void bcm2835_gpio_set(uint8_t pin);
  1070.  
  1071. /*! Sets the specified pin output to
  1072.   LOW.
  1073.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1074.   \sa bcm2835_gpio_write()
  1075.   */
  1076. extern void bcm2835_gpio_clr(uint8_t pin);
  1077.  
  1078. /*! Sets any of the first 32 GPIO output pins specified in the mask to
  1079.   HIGH.
  1080.   \param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)
  1081.   \sa bcm2835_gpio_write_multi()
  1082.   */
  1083. extern void bcm2835_gpio_set_multi(uint32_t mask);
  1084.  
  1085. /*! Sets any of the first 32 GPIO output pins specified in the mask to
  1086.   LOW.
  1087.   \param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)
  1088.   \sa bcm2835_gpio_write_multi()
  1089.   */
  1090. extern void bcm2835_gpio_clr_multi(uint32_t mask);
  1091.  
  1092. /*! Reads the current level on the specified
  1093.   pin and returns either HIGH or LOW. Works whether or not the pin
  1094.   is an input or an output.
  1095.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1096.   \return the current level either HIGH or LOW
  1097.   */
  1098. extern uint8_t bcm2835_gpio_lev(uint8_t pin);
  1099.  
  1100. /*! Event Detect Status.
  1101.   Tests whether the specified pin has detected a level or edge
  1102.   as requested by bcm2835_gpio_ren(), bcm2835_gpio_fen(), bcm2835_gpio_hen(),
  1103.   bcm2835_gpio_len(), bcm2835_gpio_aren(), bcm2835_gpio_afen().
  1104.   Clear the flag for a given pin by calling bcm2835_gpio_set_eds(pin);
  1105.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1106.   \return HIGH if the event detect status for the given pin is true.
  1107.   */
  1108. extern uint8_t bcm2835_gpio_eds(uint8_t pin);
  1109.  
  1110. /*! Sets the Event Detect Status register for a given pin to 1,
  1111.   which has the effect of clearing the flag. Use this afer seeing
  1112.   an Event Detect Status on the pin.
  1113.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1114.   */
  1115. extern void bcm2835_gpio_set_eds(uint8_t pin);
  1116.  
  1117. /*! Enable Rising Edge Detect Enable for the specified pin.
  1118.   When a rising edge is detected, sets the appropriate pin in Event Detect Status.
  1119.   The GPRENn registers use
  1120.   synchronous edge detection. This means the input signal is sampled using the
  1121.   system clock and then it is looking for a ?011? pattern on the sampled signal. This
  1122.   has the effect of suppressing glitches.
  1123.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1124.   */
  1125. extern void bcm2835_gpio_ren(uint8_t pin);
  1126.  
  1127. /*! Disable Rising Edge Detect Enable for the specified pin.
  1128.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1129.   */
  1130. extern void bcm2835_gpio_clr_ren(uint8_t pin);
  1131.  
  1132. /*! Enable Falling Edge Detect Enable for the specified pin.
  1133.   When a falling edge is detected, sets the appropriate pin in Event Detect Status.
  1134.   The GPRENn registers use
  1135.   synchronous edge detection. This means the input signal is sampled using the
  1136.   system clock and then it is looking for a ?100? pattern on the sampled signal. This
  1137.   has the effect of suppressing glitches.
  1138.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1139.   */
  1140. extern void bcm2835_gpio_fen(uint8_t pin);
  1141.  
  1142. /*! Disable Falling Edge Detect Enable for the specified pin.
  1143.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1144.   */
  1145. extern void bcm2835_gpio_clr_fen(uint8_t pin);
  1146.  
  1147. /*! Enable High Detect Enable for the specified pin.
  1148.   When a HIGH level is detected on the pin, sets the appropriate pin in Event Detect Status.
  1149.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1150.   */
  1151. extern void bcm2835_gpio_hen(uint8_t pin);
  1152.  
  1153. /*! Disable High Detect Enable for the specified pin.
  1154.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1155.   */
  1156. extern void bcm2835_gpio_clr_hen(uint8_t pin);
  1157.  
  1158. /*! Enable Low Detect Enable for the specified pin.
  1159.   When a LOW level is detected on the pin, sets the appropriate pin in Event Detect Status.
  1160.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1161.   */
  1162. extern void bcm2835_gpio_len(uint8_t pin);
  1163.  
  1164. /*! Disable Low Detect Enable for the specified pin.
  1165.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1166.   */
  1167. extern void bcm2835_gpio_clr_len(uint8_t pin);
  1168.  
  1169. /*! Enable Asynchronous Rising Edge Detect Enable for the specified pin.
  1170.   When a rising edge is detected, sets the appropriate pin in Event Detect Status.
  1171.   Asynchronous means the incoming signal is not sampled by the system clock. As such
  1172.   rising edges of very short duration can be detected.
  1173.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1174.   */
  1175. extern void bcm2835_gpio_aren(uint8_t pin);
  1176.  
  1177. /*! Disable Asynchronous Rising Edge Detect Enable for the specified pin.
  1178.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1179.   */
  1180. extern void bcm2835_gpio_clr_aren(uint8_t pin);
  1181.  
  1182. /*! Enable Asynchronous Falling Edge Detect Enable for the specified pin.
  1183.   When a falling edge is detected, sets the appropriate pin in Event Detect Status.
  1184.   Asynchronous means the incoming signal is not sampled by the system clock. As such
  1185.   falling edges of very short duration can be detected.
  1186.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1187.   */
  1188. extern void bcm2835_gpio_afen(uint8_t pin);
  1189.  
  1190. /*! Disable Asynchronous Falling Edge Detect Enable for the specified pin.
  1191.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1192.   */
  1193. extern void bcm2835_gpio_clr_afen(uint8_t pin);
  1194.  
  1195. /*! Sets the Pull-up/down register for the given pin. This is
  1196.   used with bcm2835_gpio_pudclk() to set the Pull-up/down resistor for the given pin.
  1197.   However, it is usually more convenient to use bcm2835_gpio_set_pud().
  1198.   \param[in] pud The desired Pull-up/down mode. One of BCM2835_GPIO_PUD_* from bcm2835PUDControl
  1199.   \sa bcm2835_gpio_set_pud()
  1200.   */
  1201. extern void bcm2835_gpio_pud(uint8_t pud);
  1202.  
  1203. /*! Clocks the Pull-up/down value set earlier by bcm2835_gpio_pud() into the pin.
  1204.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1205.   \param[in] on HIGH to clock the value from bcm2835_gpio_pud() into the pin.
  1206.   LOW to remove the clock.
  1207.   \sa bcm2835_gpio_set_pud()
  1208.   */
  1209. extern void bcm2835_gpio_pudclk(uint8_t pin, uint8_t on);
  1210.  
  1211. /*! Reads and returns the Pad Control for the given GPIO group.
  1212.   \param[in] group The GPIO pad group number, one of BCM2835_PAD_GROUP_GPIO_*
  1213.   \return Mask of bits from BCM2835_PAD_* from \ref bcm2835PadGroup
  1214.   */
  1215. extern uint32_t bcm2835_gpio_pad(uint8_t group);
  1216.  
  1217. /*! Sets the Pad Control for the given GPIO group.
  1218.   \param[in] group The GPIO pad group number, one of BCM2835_PAD_GROUP_GPIO_*
  1219.   \param[in] control Mask of bits from BCM2835_PAD_* from \ref bcm2835PadGroup. Note
  1220.   that it is not necessary to include BCM2835_PAD_PASSWRD in the mask as this
  1221.   is automatically included.
  1222.   */
  1223. extern void bcm2835_gpio_set_pad(uint8_t group, uint32_t control);
  1224.  
  1225. /*! Delays for the specified number of milliseconds.
  1226.   Uses nanosleep(), and therefore does not use CPU until the time is up.
  1227.   However, you are at the mercy of nanosleep(). From the manual for nanosleep():
  1228.   If the interval specified in req is not an exact multiple of the granularity
  1229.   underlying clock (see time(7)), then the interval will be
  1230.   rounded up to the next multiple. Furthermore, after the sleep completes,
  1231.   there may still be a delay before the CPU becomes free to once
  1232.   again execute the calling thread.
  1233.   \param[in] millis Delay in milliseconds
  1234.   */
  1235. extern void bcm2835_delay (unsigned int millis);
  1236.  
  1237. /*! Delays for the specified number of microseconds.
  1238.   Uses a combination of nanosleep() and a busy wait loop on the BCM2835 system timers,
  1239.   However, you are at the mercy of nanosleep(). From the manual for nanosleep():
  1240.   If the interval specified in req is not an exact multiple of the granularity
  1241.   underlying clock (see time(7)), then the interval will be
  1242.   rounded up to the next multiple. Furthermore, after the sleep completes,
  1243.   there may still be a delay before the CPU becomes free to once
  1244.   again execute the calling thread.
  1245.   For times less than about 450 microseconds, uses a busy wait on the System Timer.
  1246.   It is reported that a delay of 0 microseconds on RaspberryPi will in fact
  1247.   result in a delay of about 80 microseconds. Your mileage may vary.
  1248.   \param[in] micros Delay in microseconds
  1249.   */
  1250. extern void bcm2835_delayMicroseconds (uint64_t micros);
  1251.  
  1252. /*! Sets the output state of the specified pin
  1253.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1254.   \param[in] on HIGH sets the output to HIGH and LOW to LOW.
  1255.   */
  1256. extern void bcm2835_gpio_write(uint8_t pin, uint8_t on);
  1257.  
  1258. /*! Sets any of the first 32 GPIO output pins specified in the mask to the state given by on
  1259.   \param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)
  1260.   \param[in] on HIGH sets the output to HIGH and LOW to LOW.
  1261.   */
  1262. extern void bcm2835_gpio_write_multi(uint32_t mask, uint8_t on);
  1263.  
  1264. /*! Sets the first 32 GPIO output pins specified in the mask to the value given by value
  1265.   \param[in] value values required for each bit masked in by mask, eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)
  1266.   \param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)
  1267.   */
  1268. extern void bcm2835_gpio_write_mask(uint32_t value, uint32_t mask);
  1269.  
  1270. /*! Sets the Pull-up/down mode for the specified pin. This is more convenient than
  1271.   clocking the mode in with bcm2835_gpio_pud() and bcm2835_gpio_pudclk().
  1272.   \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
  1273.   \param[in] pud The desired Pull-up/down mode. One of BCM2835_GPIO_PUD_* from bcm2835PUDControl
  1274.   */
  1275. extern void bcm2835_gpio_set_pud(uint8_t pin, uint8_t pud);
  1276.  
  1277. /*! @} */
  1278.  
  1279. /*! \defgroup spi SPI access
  1280.   These functions let you use SPI0 (Serial Peripheral Interface) to
  1281.   interface with an external SPI device.
  1282.   @{
  1283.   */
  1284.  
  1285. /*! Start SPI operations.
  1286.   Forces RPi SPI0 pins P1-19 (MOSI), P1-21 (MISO), P1-23 (CLK), P1-24 (CE0) and P1-26 (CE1)
  1287.   to alternate function ALT0, which enables those pins for SPI interface.
  1288.   You should call bcm2835_spi_end() when all SPI funcitons are complete to return the pins to
  1289.   their default functions
  1290.   \sa bcm2835_spi_end()
  1291.   */
  1292. extern void bcm2835_spi_begin(void);
  1293.  
  1294. /*! End SPI operations.
  1295.   SPI0 pins P1-19 (MOSI), P1-21 (MISO), P1-23 (CLK), P1-24 (CE0) and P1-26 (CE1)
  1296.   are returned to their default INPUT behaviour.
  1297.   */
  1298. extern void bcm2835_spi_end(void);
  1299.  
  1300. /*! Sets the SPI bit order
  1301.   NOTE: has no effect. Not supported by SPI0.
  1302.   Defaults to
  1303.   \param[in] order The desired bit order, one of BCM2835_SPI_BIT_ORDER_*,
  1304.   see \ref bcm2835SPIBitOrder
  1305.   */
  1306. extern void bcm2835_spi_setBitOrder(uint8_t order);
  1307.  
  1308. /*! Sets the SPI clock divider and therefore the
  1309.   SPI clock speed.
  1310.   \param[in] divider The desired SPI clock divider, one of BCM2835_SPI_CLOCK_DIVIDER_*,
  1311.   see \ref bcm2835SPIClockDivider
  1312.   */
  1313. extern void bcm2835_spi_setClockDivider(uint16_t divider);
  1314.  
  1315. /*! Sets the SPI data mode
  1316.   Sets the clock polariy and phase
  1317.   \param[in] mode The desired data mode, one of BCM2835_SPI_MODE*,
  1318.   see \ref bcm2835SPIMode
  1319.   */
  1320. extern void bcm2835_spi_setDataMode(uint8_t mode);
  1321.  
  1322. /*! Sets the chip select pin(s)
  1323.   When an bcm2835_spi_transfer() is made, the selected pin(s) will be asserted during the
  1324.   transfer.
  1325.   \param[in] cs Specifies the CS pins(s) that are used to activate the desired slave.
  1326.   One of BCM2835_SPI_CS*, see \ref bcm2835SPIChipSelect
  1327.   */
  1328. extern void bcm2835_spi_chipSelect(uint8_t cs);
  1329.  
  1330. /*! Sets the chip select pin polarity for a given pin
  1331.   When an bcm2835_spi_transfer() occurs, the currently selected chip select pin(s)
  1332.   will be asserted to the
  1333.   value given by active. When transfers are n
Compilation error #stdin compilation error #stdout 0s 0KB
stdin
Standard input is empty
compilation info
prog.cpp:1330:5: error: unterminated comment
     /*! Sets the chip select pin polarity for a given pin
     ^
prog.cpp:380:0: error: unterminated #ifndef
 #ifndef BCM2835_H
 ^
prog.cpp:1328:51: error: expected '}' at end of input
     extern void bcm2835_spi_chipSelect(uint8_t cs);
                                                   ^
stdout
Standard output is empty